Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl2 and BCl3.

Abstract: A method for manufacturing the semiconductor device includes: providing a layer to be etched; on a surface of the layer to be etched, forming a first sacrificial layer that is patterned and includes an opening for exposing the layer to be etched; forming a second sacrificial layer in the opening, the second sacrificial layer having a contact face contacted with the first sacrificial layer; forming a third sacrificial layer via a reaction between the first sacrificial layer and the second sacrificial layer at the contact face; removing at least one of at least part of an unreacted portion of the first sacrificial layer and the second sacrificial layer to form a patterned mask structure; etching the layer to be etched based on the patterned mask structure to form an etched pattern.

Abstract: An e-beam device includes a cold-field emission source to emit electrons and an extractor electrode to be positively biased with respect to the cold-field emission source to extract the electrons from the cold-field emission source. The extractor electrode has a first opening for the electrons. The e-beam device also includes a mirror electrode with a second opening for the electrons. The mirror electrode is configurable to be positively biased with respect to the extractor electrode during a first mode of operation and to be negatively biased with respect to the extractor electrode during a second mode of operation. The extractor electrode is disposed between the cold-field emission source and the mirror electrode. The e-beam device further includes an anode to be positively biased with respect to the extractor electrode and the cold-field emission source. The mirror electrode is disposed between the extractor electrode and the anode.

Abstract: A method for treating a flexible plastic substrate is provided herein. The method includes establishing an atmospheric pressure plasma beam from an inert gas using a power of greater than about 90W, directing the plasma beam toward a surface of the flexible polymer substrate, and scanning the plasma beam across the surface of the polymer substrate to form a treated substrate surface.

Abstract: A method, apparatus and system for processing a wafer in a plasma chamber system, which includes at least a plasma generating element and a biasing electrode, include generating a plasma in the plasma chamber system by applying a source RF source power to the plasma generating element for a first period of time of a pulse period of the RF source power, after the expiration of the first period of time, removing the source RF source power, after a delay after the removal of the RF source power, applying an RF bias signal to the biasing electrode for a second period of time to bias the generated plasma towards the wafer, and after the expiration of the second period of time, removing the RF bias signal from the biasing electrode before a next pulse period of the RF source power. The generated plasma biased toward the wafer is used to process the wafer.

Abstract: A substrate processing system includes a first main surface grinding device configured to grind, while holding a substrate from below with a first main surface of the substrate facing upwards, the first main surface of the substrate; a first inverting device configured to invert the substrate ground by the first main surface grinding device; and a second main surface grinding device configured to grin, while holding the ground first main surface of the substrate from below with a second main surface of the substrate facing upwards, the second main surface of the substrate.

Abstract: A novel method for producing a novel electro-optic electric-field sensor is disclosed. The resulting end product from this production method is a unique electro-optic electric-field sensor that includes thin film optical waveguides made from an electro-optic material on a low dielectric constant substrate. An optical circuit fabricated utilizing this production method may be a Mach-Zehnder interferometer or a micro-ring modulator. The low dielectric constant substrate allows the electric field to have high strength in the electro-optic thin film section, which in turn enables high sensitivity. In addition, for the Mach-Zehnder modulator sensor structure, phase matching is achieved between the RF or THz signal and the optical signal, resulting in an ultra-high-speed sensor for detection of Terahertz (THz) e-fields. An alternative design with a micro-ring electric-field sensor structure is also disclosed for high-spatial resolution electric-field sensing applications.

Abstract: An etching method includes mounting a substrate on a stage in a processing chamber, the substrate including a laminate film. The etching method includes supplying process gas to the processing chamber, the process gas including at least one of fluorocarbon gas or hydrofluorocarbon gas. The etching method includes selecting, based on a combination of material of a silicon-containing insulating layer and material of an underlying layer, a surface temperature range of at least one member of a first member or a second member in the processing chamber, the first member facing the substrate, and the second member being provided to encircle the substrate. The etching method includes adjusting a surface temperature of the one member to be within the selected surface temperature range. The etching method includes forming a plasma in the processing chamber to which the process gas is supplied, thereby etching the silicon-containing insulating layer.

Abstract: An etching method of forming, on a substrate having a base film; a stacked film in which a first film and a second film are alternately stacked on the base film; and a mask on the stacked film, a recess in the stacked film through the mask by using plasma includes preparing the substrate; and etching the stacked film until the recess of the stacked film reaches the base film by plasma formed from a gas containing hydrogen, fluorine and carbon, while maintaining a substrate temperature equal to or less than 15° C.

Abstract: The invention provides a chemical-mechanical polishing composition comprising: (a) a silica abrasive, (b) a surfactant, (c) an iron cation, (d) optionally a ligand, and (e) water, wherein the silica abrasive has a negative zeta potential in the chemical-mechanical polishing composition. The invention also provides a method of chemically-mechanically polishing a substrate, especially a substrate comprising a carbon-based film, using said composition.

Abstract: A method of depositing a silicon-containing material is disclosed. Some embodiments of the disclosure provide films which fill narrow CD features without a seam or void. Some embodiments of the disclosure provide films which form conformally on features with wider CD. Embodiments of the disclosure also provide superior quality films with low roughness, low defects and advantageously low deposition rates.

Abstract: A hollow cathode includes an insulation plate having cathode holes. Bottom electrodes are below the insulation plate. The bottom electrodes define first holes having a width greater than a width of the cathode holes. Top electrodes are at an opposite side of the insulation plate from the bottom electrodes. The top electrodes define second holes aligned with the first holes along a direction orthogonal to the upper surface of the insulation plate.

Abstract: A pattern forming method includes: forming a first film on a first region of a processing target film; forming a second film containing metal and carbon and different from the first film, on a second region of the processing target film; etching the first film; and etching the processing target film using the first film after the etching while the second film is exposed.

Abstract: A manufacturing method of a semiconductor structure includes: providing a target layer; forming a plurality of first mask patterns on a top surface of the target layer; forming a plurality of second mask patterns above the target layer, where each of the second mask patterns covers at least a part of a top surface of each of the first mask patterns and a part of the top surface of the target layer in an extension direction of the second mask pattern; performing a first etching on the target layer based on the second mask patterns; removing the second mask patterns; and performing a second etching on the target layer based on the first mask patterns.

Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

Abstract: A method for preparing suspended graphene support film by selectively etching growth substrate is disclosed in present invention. The transfer process of graphene is avoided. The process of present invention is efficient and low in cost, suspended graphene support film can be prepared in a single etching step. The prepared graphene support film does not need any support by polymer film and polymer fiber. The prepared graphene support film has controllable number of layers and high intactness (90%-97%), large suspended area (diameter is 10-50 ?m), wide clean area (>100 nm) and can be mass-produced. In addition, the graphene support film can be directly used as transmission electron microscope support film, and can be used to achieve high resolution imaging of nanoparticles.

Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.

Abstract: A CMP slurry composition for copper films and a method of polishing a copper film using the same are disclosed, the composition including a polar solvent or a non-polar solvent; and polishing particles modified with a silicon-containing compound, wherein the silicon-containing compound is represented by Formula 1,

Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.

Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.