Patents Examined by Roberts Culbert
  • Patent number: 9922923
    Abstract: To provide a technique capable of easily forming a resin opening of a desired shape. As a solution, a base is prepared which has a first surface region and a second surface region around the first surface region, and which has a wiring formed thereon. Subsequently, a resist which covers the first surface region is formed. Then, the first surface region and the second surface region are covered with a resin body such that the resist is included therein, and the resist is exposed from the resin body. After that, the exposed resist is removed, so that a resin opening that exposes the base in the first surface region is formed in the resin body.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: March 20, 2018
    Assignee: KABUSHIKI KAISHA EASTERN
    Inventor: Yoshiaki Narisawa
  • Patent number: 9919916
    Abstract: A method of forming microneedles where through a series of coating and etching processes microneedles are formed from a surface as an array. The microneedles have a bevelled end and bore which are formed as part of the process with no need to use a post manufacturing process to finish the microneedle.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: March 20, 2018
    Assignee: Semitechnologies Llimited
    Inventors: Yufei Lui, Owen Guy
  • Patent number: 9914852
    Abstract: The present disclosure provides a method for reducing large particle counts (LPCs) in copper chemical mechanical polishing slurry by way of using high purity removal rate enhancer (RRE) in the slurry. The conductivity of the RRE in deionized water solutions correlates very strongly with the number of LPCs in the RRE, and thus in a slurry using the RRE.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: March 13, 2018
    Assignee: FUJIFILM PLANAR SOLUTIONS, LLC
    Inventors: James McDonough, Laura John, Deepak Mahulikar
  • Patent number: 9911648
    Abstract: A method for forming at least one Ag or Ag based alloy feature in an integrated circuit, including providing a blanket layer of Ag or Ag based alloy in a multi-layer structure on a substrate. The method further includes providing a hard mask layer over the blanket layer of Ag or Ag based alloy. The method further includes performing an etch of the blanket layer of Ag or Ag based alloy, wherein a portion of the blanket layer of Ag or Ag based alloy that remains after the etch forms one or more conductive lines. The method further includes forming a liner that surrounds the one or more conductive lines. The method further includes depositing a dielectric layer on the multi-layer structure.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brett C. Baker-O'Neal, Eric A. Joseph, Hiroyuki Miyazoe
  • Patent number: 9911617
    Abstract: The invention discloses a novel dry etching method, which comprises the following steps: forming a to-be-etched layer on a semiconductor substrate; forming a masking material on the to-be-etched layer; carrying out dry etching on the masking material and the to-be-etched layer; simultaneously carrying out lateral etching (parallel to the surface of the substrate) of a masking layer and longitudinal etching (vertical to the surface of the substrate) of the to-be-etched layer; and obtaining the inclination angle (the included angle between a slope surface and the surface of the substrate) of the corresponding etched slope surface by accurately controlling the speed ratio. The method can flexibly adjust the inclination angle of the etched slope surface within a large range (0-90 degrees), and especially has advantages in the field of the application with a small inclination angle (smaller than 20 degrees) of the etched slope surface in comparison with a conventional etching method.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: March 6, 2018
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Junjie Li, Junfeng Li, Qinghua Yang, Jinbiao Liu, Xiaobin He
  • Patent number: 9911604
    Abstract: Disclosed are methods of using a lithography-lithography-etch (LLE) technique to form a sidewall spacer pattern for patterning a target layer. In the methods, a photoresist layer is patterned by performing multiple lithographic processes with different photomasks, including a first photomask with a first pattern of parallel bars separated by spaces and a second photomask with a second pattern of opening(s) oriented in an essentially perpendicular direction as compared to the bar(s). The photoresist layer is then developed, creating a third pattern. The third pattern is transferred into a mandrel layer below to form mandrels of different lengths. Then, sidewall spacers are formed on the mandrels and the mandrels are selectively removed to form the sidewall spacer pattern. This sidewall spacer pattern is subsequently used in a sidewall image transfer (SIT) process to pattern a target layer below.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: March 6, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Sun, Xunyuan Zhang, Ruilong Xie, Yulu Chen
  • Patent number: 9896770
    Abstract: Provided are methods for etching films comprising transition metals which help to minimize higher etch rates at the grain boundaries of polycrystalline materials. Certain methods pertain to amorphization of the polycrystalline material, other pertain to plasma treatments, and yet other pertain to the use of small doses of halide transfer agents in the etch process.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: February 20, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Benjamin Schmiege, Nitin K. Ingle, Srinivas D. Nemani, Jeffrey W. Anthis, Xikun Wang, Jie Liu, David Benjaminson
  • Patent number: 9892915
    Abstract: A manufacturing method of a semiconductor device includes forming a hard mask layer on a semiconductor substrate using a hard mask composition. Hard mask patterns are formed by patterning the hard mask layer. Semiconductor patterns are formed by etching the semiconductor substrate using the hard mask patterns. The hard mask composition includes a plurality of first carbon nanotubes (CNTs) having a first length, a plurality of second CNTs having a second length, which is at least 3 times the first length, and a dispersing agent in which the first CNTs and the second CNTs are dispersed. The total mass of the first CNTs is 1 to 2.5 times the total mass of the second CNTs.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: February 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Yun Yang, Seung Hyun Lee, Kyoung Sil Park, Yool Kang, Yi Seul Kim, Yun Seok Choi
  • Patent number: 9887109
    Abstract: A plasma etching method includes a holding step of holding a substrate, a processing gas supplying step of supplying processing gas to a space between the holding unit and an electrode plate facing the holding unit within the processing chamber, and a high frequency power supplying step of converting the processing gas supplied to the space from the plurality of supply parts into plasma by supplying a high frequency power from a high frequency power supply to at least one of the holding unit and the electrode plate. The processing gas supplying step includes controlling an adjustment unit configured to adjust a supply condition for supplying processing gas with respect to each of the plurality of supply parts such that the supply condition that is adjusted varies between a first position and a second position.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: February 6, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Masaya Kawamata, Masanobu Honda, Kazuhiro Kubota
  • Patent number: 9873833
    Abstract: Etching compositions and method of using the etching compositions comprising potassium hydroxide; one or more than one additional alkaline compounds selected from the group consisting of TEAH, TMAF and NH4OH; and water; or etching compositions comprising one or more than one inorganic alkali basic hydroxides selected from the group consisting of potassium hydroxide, cesium hydroxide, sodium hydroxide, rubidium hydroxide, or lithium hydroxide; optionally one or more than one additional alkaline compounds; water; and optionally one or more corrosion inhibitors; wherein the composition preferentially etches silicon present on a substrate as compared to silicon dioxide present on said substrate.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 23, 2018
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Gene Everad Parris, William Jack Casteel, Jr., Tianniu Rick Chen
  • Patent number: 9874694
    Abstract: A plurality of Bragg gratings are formed at predetermined locations of a laminate including a mounting substrate, a clad layer provided on the mounting substrate and an optical material layer provided on the clad layer. Optical waveguides are formed each including at least each of the Bragg gratings. Masks are formed each covering a region corresponding to each of the grating elements on the optical material layer. The optical material layer and clad layer are etched to shape an end face of each of the grating elements.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: January 23, 2018
    Assignee: NGK Insulators, Ltd.
    Inventors: Keiichiro Asai, Shoichiro Yamaguchi, Jungo Kondo, Naotake Okada, Tetsuya Ejiri
  • Patent number: 9870915
    Abstract: Embodiments include a method of processing a hardmask that includes forming an alloyed carbon hardmask over an underlying layer. In an embodiment, the alloyed carbon hardmask is alloyed with metallic-carbon fillers. The embodiment further includes patterning the alloyed carbon hardmask and transferring the pattern of the alloyed carbon hardmask into the underlying layer. According to an embodiment, the method may further include removing the metallic component of the metallic-carbon fillers from the alloyed carbon hardmask to form a porous carbon hardmask. Thereafter, the porous hardmask may be removed. In an embodiment, the metallic component of the metallic-carbon fillers may include flowing a processing gas into a chamber that volatizes the metallic component of the metallic-carbon fillers.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: January 16, 2018
    Assignee: Applied Materials, Inc.
    Inventors: David Knapp, Simon Huang, Jeffrey W. Anthis, Philip Alan Kraus, David Thompson
  • Patent number: 9865474
    Abstract: An etching method using plasma includes generating plasma by supplying process gases to at least one remote plasma source (RPS) and applying power to the at least one RPS, and etching an etching object by supplying water (H2O) and the plasma to a process chamber.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: January 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gon-jun Kim, Vladimir Volynets, Sang-jin An, Hee-jeon Yang, Sangheon Lee, Sung-keun Cho, Xinglong Chen, In-ho Choi
  • Patent number: 9862189
    Abstract: There is provided a method for forming a smooth resin layer on a substrate having a concavo-convex portion in manufacturing a liquid ejection head by a casting method. To achieve this, after forming an opening pattern on the resin layer formed on the substrate, a mold is brought into contact with the resin layer at a predetermined pressure so as to smooth a surface of the resin layer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 9, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Akihiko Okano, Takumi Suzuki, Tamaki Sato
  • Patent number: 9865472
    Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: January 9, 2018
    Assignee: Lam Research Corporation
    Inventors: Robert Chebi, Frank Lin, Jaroslaw W. Winniczek, Wan-Lin Chen, Erin Moore, Lily Zheng, Stephan Lassig, Jeff Bogart, Camelia Rusu
  • Patent number: 9865804
    Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask over a selected portion of the third layer of ferromagnetic material, wherein the mask is a metal hard mask. Thereafter, etching through the third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure, through the second tunnel barrier layer to form a second tunnel barrier and provide sidewalls thereof and the second layer of ferromagnetic material to provide sidewalls thereof. Thereafter, etching, through the first tunnel barrier layer to form a first tunnel barrier to provide sidewalls thereof and etching the first layer of ferromagnetic material to provide sidewalls thereof. The process may then include oxidizing the sidewalls of (i) the first tunnel barrier and (ii) the first layer of ferromagnetic material.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: January 9, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel
  • Patent number: 9859111
    Abstract: In one embodiment, an apparatus of treating a surface of a semiconductor substrate comprises a substrate holding and rotating unit, first to fourth supplying units, and a removing unit. A substrate holding and rotating unit holds a semiconductor substrate, having a convex pattern formed on its surface, and rotates the semiconductor substrate. A first supplying unit supplies a chemical onto the surface of the semiconductor substrate in order to clean the semiconductor substrate. A second supplying unit supplies pure water to the surface of the semiconductor substrate in order to rinse the semiconductor substrate. A third supplying unit supplies a water repellent agent to the surface of the semiconductor substrate in order to form a water repellent protective film onto the surface of the convex pattern. A fourth supplying unit supplies alcohol, which is diluted with pure water, or acid water to the surface of the semiconductor substrate in order to rinse the semiconductor substrate.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: January 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshihiro Ogawa, Tatsuhiko Koide, Shinsuke Kimura, Hisashi Okuchi, Hiroshi Tomita
  • Patent number: 9852891
    Abstract: A method for efficient plasma etching of surfaces inside three-dimensional structures can include positioning an inner electrode within the chamber cavity; evacuating the chamber cavity; adding a first inert gas to the chamber cavity; regulating the pressure in the chamber; generating a plasma sheath along the inner wall of the chamber cavity; adjusting a positive D.C. bias on the inner electrode to establish an effective plasma sheath voltage; adding a first electronegative gas to the chamber cavity; optionally readjusting the positive D.C. bias on the inner electrode reestablish the effective plasma sheath voltage at the chamber cavity; etching the inner wall of the chamber cavity; and polishing the inner wall to a desired surface roughness.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: December 26, 2017
    Assignee: Old Dominion University Research Foundation
    Inventors: Svetozar Popovic, Janardan Upadhyay, Leposava Vuskovic, H. Lawrence Phillips, Anne-Marie Valente-Feliciano
  • Patent number: 9852922
    Abstract: A plasma etching method includes: mounting a target substrate on a first electrode which is provided to be parallel with a second electrode with a preset gap within a processing chamber, a base material of the second electrode containing silicon or SiC; generating plasma of a fluorocarbon-based etching gas in a processing space; applying a low frequency AC power or a high frequency AC power having a frequency, which an ion in the plasma is allowed to follow, to the second electrode; and increasing an effective voltage value of the AC power to enhance sputtering at the second electrode such that silicon sputtered from the base material reacts with fluorine radicals generated from the fluorocarbon-based etching gas to produce a reaction product of SiF4, to irradiate electrons generated near the second electrode to the target substrate and to increase a plasma potential near a sidewall of the processing chamber.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 26, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hikaru Watanabe, Masanobu Honda
  • Patent number: 9852920
    Abstract: Provided are a method and system for increasing etch rate and etch selectivity of a masking layer on a substrate in an etch treatment system, the etch treatment system configured for single substrate processing. The method comprises placing the substrate into the etch processing chamber, the substrate containing the masking layer and a layer of silicon or silicon oxide, obtaining a supply of steam water vapor mixture at elevated pressure, obtaining a supply of treatment liquid for selectively etching the masking layer over the silicon or silicon oxide at a selectivity ratio, combining the treatment liquid and the steam water vapor mixture, and injecting the combined treatment liquid and the steam water vapor mixture into the etch processing chamber. The flow of the combined treatment liquid and the steam water vapor mixture is controlled to maintain a target etch rate and a target etch selectivity ratio of the masking layer to the layer of silicon or silicon oxide.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: December 26, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Ian J. Brown, Wallace P. Printz