Patents Examined by Roberts Culbert
  • Patent number: 9768034
    Abstract: Exemplary cleaning or etching methods may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. Methods may include forming a plasma within the remote plasma region to generate plasma effluents of the fluorine-containing precursor. The methods may also include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned within the processing region, and the substrate may include a region of exposed oxide. Methods may also include providing a hydrogen-containing precursor to the processing region. The methods may further include removing at least a portion of the exposed oxide while maintaining a relative humidity within the processing region below about 50%. Subsequent to the removal, the methods may include increasing the relative humidity within the processing region to greater than or about 50%. The methods may further include removing an additional amount of the exposed oxide.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: September 19, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Lin Xu, Zhijun Chen, Jiayin Huang, Anchuan Wang
  • Patent number: 9761452
    Abstract: Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: September 12, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jiehui Shu, Daniel Jaeger, Garo Jacques Derderian, Haifeng Sheng, Jinping Liu
  • Patent number: 9758698
    Abstract: Provided are slurry for polishing cobalt and a substrate polishing method. The slurry includes an abrasive configured to perform the polishing, the abrasive comprising zirconium oxide particles, a dispersing agent configured to disperse the abrasive, and a polishing accelerator configured to accelerate the polishing. The polishing accelerator includes an organic acid containing an amine group and a carboxylic group. According to the slurry in accordance with an exemplary embodiment, a polishing rate of the cobalt may increases without using an oxidizing agent, and local corrosion defects on a surface of the cobalt may be suppressed.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: September 12, 2017
    Assignee: UBMATERIALS INC.
    Inventor: Jin Hyung Park
  • Patent number: 9752057
    Abstract: A chemical mechanical polishing (CMP) method for removal of a metal layer deposited over a titanium nitride (TiN) or titanium/titanium nitride (Ti/TiN) barrier layer is described herein. The method comprises abrading the metal layer with an acidic CMP composition to expose the underlying TiN or Ti/TiN layer, wherein the TiN or Ti/N layer is polished at a low rate due to the presence of a surfactant inhibitor. The acidic CMP composition comprises a particulate abrasive (e.g., silica, alumina) suspended in a liquid carrier containing a surfactant selected from the group consisting of an anionic surfactant, a nonionic surfactant, cation surfactants, and a combination thereof.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: September 5, 2017
    Assignee: Cabot Microelectronics Corporation
    Inventors: Hui-Fang Hou, William Ward, Ming-Chih Yeh, Chih-Pin Tsai
  • Patent number: 9745220
    Abstract: A method etching a glass material comprises providing an etchant comprising 10-30% HF, 5-15% HNO3,and at least 10% H3PO4 by volume constituted such that the ratio HF:HNO3 by volume is in the range of 1.7:1 to 2.3:1, providing a glass material to be etched, and contacting the glass material with the etchant. The etchant desirably has no other acid components. The method may be performed with the etchant temperature within the range of 20-30° C. The glass material may be an aluminosilicate glass. Ultrasound energy may be applied to the etchant, to the glass material, or both.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: August 29, 2017
    Assignee: Corning Incorporated
    Inventors: Robert Carl Burket, Benedict Yorke Johnson, Samuel Odei Owusu, Tammy Lynn Petriwsky
  • Patent number: 9741567
    Abstract: Disclosed herein is a method of forming a structure, comprising forming a mandrel layer over a substrate, masking the mandrel layer with a first mask and performing a first etch on the mandrel layer, the first etch forming a first opening exposing a first portion of the substrate. The mandrel layer is masked with a second mask and a second etch is performed on the mandrel layer. The second etch forms a second opening exposing a second portion of the substrate, and also forms a protective layer on the first portion of the substrate and in the first opening.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Shau-Lin Shue
  • Patent number: 9740174
    Abstract: The invention relates to a method for fabrication of a one-piece, silicon-based component of simple shape offering the illusion of faceting and/or chamfering for forming all or part of the exterior part of a timepiece.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: August 22, 2017
    Assignee: Nivarox-FAR S.A.
    Inventors: Pierre Cusin, Alex Gandelhman, Michel Musy
  • Patent number: 9734989
    Abstract: A film thickness distribution exists in a substrate plane after CMP step. This film thickness distribution results in, for example, variation in gate threshold value voltages of metal gates, and causes variation in element characteristics. It is an object of the present invention to easily improve the film thickness distribution processed by this CMP step. By using the ion beam etching method after the CMP step, the film thickness distribution in the plane of the substrate 111 is corrected. More specifically, when the ion beam etching is performed, the plasma density in the plasma generation chamber 102 is caused to be different between a position facing a central portion in the plane of the substrate 111 and a position facing an outer peripheral portion, so that the etching rate in the central portion in the plane of the substrate 111 and the etching rate in the outer peripheral portion in the substrate plane 111 are caused to be different.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: August 15, 2017
    Assignee: CANON ANELVA CORPORATION
    Inventors: Yoshimitsu Kodaira, Yukito Nakagawa, Motozo Kurita
  • Patent number: 9735025
    Abstract: A method of etching a first region including a multilayered film, in which first dielectric films and second dielectric films serving as silicon nitride films are alternately stacked, and a second region including a single-layered silicon oxide film is provided. The etching method includes a first plasma process of generating plasma of a first processing gas containing a fluorocarbon gas and an oxygen gas within a processing vessel of a plasma processing apparatus; and a second plasma process of generating plasma of a second processing gas containing a hydrogen gas, nitrogen trifluoride gas and a carbon-containing gas within the processing vessel. A temperature of an electrostatic chuck is set to a first temperature in the first plasma process, and the temperature of the electrostatic chuck is set to a second temperature lower than the first temperature in the second plasma process.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 15, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masayuki Sawataishi, Tomonori Miwa, Yuki Kaneko
  • Patent number: 9735031
    Abstract: The present disclosure relates to polishing compositions that can polish Cobalt (Co) films in semiconductor substrates containing a multitude of films including Co, metals, metal oxides and dielectrics. These polishing compositions comprise an abrasive, a weak acid acting as a removal rate enhancer (RRE), a pH adjuster, and an azole-containing corrosion inhibitor (CI). The RRE, pH adjuster and CI have a pKa in the 1-18 range (1 (pKamin)<pKa<18 (pKamax)). The pKa values of the individual components are related to the pH of the polishing composition/slurry (pHslurry) by the following equation: pKamin+6<pHslurry<pKamax?6. The polishing composition also has less than about 100 parts per million (ppm) of sulfate ions and less than about 100 ppm of halide ions, and operates in the 7-12 pH range.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: August 15, 2017
    Assignee: FUJIFILM PLANAR SOLUTIONS, LLC
    Inventors: Luling Wang, Abhudaya Mishra, Deepak Mahulikar, Richard Wen
  • Patent number: 9735030
    Abstract: The present disclosure relates to polishing compositions that can polish Cobalt (Co) films in semiconductor substrates containing a multitude of films including Co, metals, metal oxides and dielectrics. These polishing compositions comprise an abrasive, a weak acid acting as a removal rate enhancer (RRE), a pH adjuster, and an azole-containing corrosion inhibitor (CI). The RRE, pH adjuster and CI have a pKa in the 1-18 range (1 (pKamin)<pKa<18 (pKamax)). The pKa values of the individual components are related to the pH of the polishing composition/slurry (pHslurry) by the following equation: pKamin+6<pHslurry<pKamax?6. The polishing composition also has less than about 100 parts per million (ppm) of sulfate ions and less than about 100 ppm of halide ions, and operates in the 7-12 pH range.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: August 15, 2017
    Assignee: FUJIFILM PLANAR SOLUTIONS, LLC
    Inventors: Luling Wang, Abhudaya Mishra, Deepak Mahulikar, Richard Wen
  • Patent number: 9725621
    Abstract: CMP processes, tools and slurries utilize composite particles that include core particles having organosilica particles disposed about the core particles. Using these processes, tools and slurries can enhance removal rates, reduce defectivity and increase cleanability with respect to comparable systems and substrates.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: August 8, 2017
    Assignee: Cabot Corporation
    Inventors: Qingling Zhang, Bennett Greenwood, Ravi Sharma, Geoffrey D. Moeser, Brian G. Prevo, Mark J. Hampden-Smith
  • Patent number: 9718710
    Abstract: According to one embodiment, a treatment apparatus includes a dialysis unit, a treatment unit and a recovery unit. The dialysis unit is configured to dialyze a solution including a phosphoric acid, a silicon compound, and water. The treatment unit is configured to perform treatment of an object to be treated using a dialyzed solution. The recovery unit is configured to recover a solution used in the treatment of the object to be treated and supply to the dialysis unit. The dialysis unit includes a transmission part which allows anions to be transmitted. The recovery unit supplies the solution used in the treatment of the object to be treated, to a region in the dialysis unit. The region is divided by the transmission part.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: August 1, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaaki Hirakawa, Emi Matsui
  • Patent number: 9720318
    Abstract: A masked etching process can prepare patterned nanocellulose for use in conformal electronics such as electrodermal structures might be adhered to human skin.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: August 1, 2017
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Michael A. Daniele, Jonathan D. Yuen
  • Patent number: 9721766
    Abstract: A method for processing a target object includes a formation step of forming a silicon oxide film in a processing chamber by repeatedly executing a sequence including a first step of supplying a first gas containing aminosilane-based gas, a second step of purging a space in the processing chamber after the first step, a third step of generating a plasma of a second gas containing oxygen gas after the second step, and a fourth step of purging the space after the third step. The method further includes a preparation step executed before the target object is accommodated in the processing chamber and a processing step of performing an etching process on the target object. The preparation step is performed before the processing step. The formation step is performed in the preparation step and the processing step. In the first step, a plasma of the first gas is not generated.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: August 1, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihide Kihara, Toru Hisamatsu, Masanobu Honda, Tomoyuki Oishi
  • Patent number: 9711423
    Abstract: A via hole is accurately formed in an interlayer insulating film over a metal wiring. Of emission spectra of plasma to be used for dry etching of the interlayer insulating film, the emission intensities of at least CO, CN, and AlF are monitored such that an end point of the dry etching of the interlayer insulating film is detected based on the emission intensities thereof.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: July 18, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Toshikazu Hanawa, Kazuhide Fukaya, Kentaro Yamada
  • Patent number: 9701902
    Abstract: An etching method according to an embodiment includes forming a catalyst layer made of a noble metal on a structure made of a semiconductor, and dipping the structure in an etching solution containing hydrofluoric acid, an oxidizer, and an organic additive to remove a portion of the structure that is in contact with the catalyst layer.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yusaku Asano
  • Patent number: 9697990
    Abstract: Provided is a method of plasma etching on a substrate using an etchant gas mixture to meet integration objectives, the method comprising: disposing a substrate having a structure pattern layer, a neutral layer, and an underlying layer, the structure pattern layer comprising a first material and a second material and the underlying layer comprising a silicon anti-reflective (SiARC) layer, a spin-on carbon hardmask (CHM) layer, an oxide layer, and a target layer; performing an first etch process to selectively remove the second material and the neutral layer using a first etchant gas mixture to form a first pattern; performing an second etch process to selectively remove the SiARC layer to form a second pattern; performing an third etch process to selectively remove the CHM layer to form a third pattern; concurrently controlling selected two or more operating variables wherein the first etchant gas include oxygen and sulfur-containing gases.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: July 4, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Satoru Nakamura, Akiteru Ko
  • Patent number: 9698341
    Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using a plurality of masks. The magnetoresistive-based device includes magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer. In one embodiment, the method may include removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first mask, to form a first electrode and a first magnetic materials, respectively, and removing the tunnel barrier layer and the second magnetic materials layer unprotected by a second mask to form a tunnel barrier and second magnetic materials, and the second electrically conductive layer unprotected by the second mask to form, and a second electrode.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 4, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal
  • Patent number: 9695347
    Abstract: Provided is a slurry composition for chemical mechanical polishing (CMP) of a metal. The slurry composition comprises a copolymer whose average molecular weight is from about 600,000 to about 1,300,000 and whose monomers are acrylic acid and acrylamide in a molar ratio of about 1:30 to about 30:1. The slurry composition exhibits a non-Prestonian behavior to achieve minimized dishing and attain a high degree of planarization.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: July 4, 2017
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Homer Chou, Won Lae Kim, Jong Il Noh, In Kyung Lee, Tae Young Lee