Patents Examined by Roberts P Culbert
  • Patent number: 10727071
    Abstract: Provided is a method of analyzing metal contamination of a silicon wafer, the method including etching a surface layer region of the silicon wafer by bringing a surface of a silicon wafer to be analyzed into contact with etching gas that includes hydrogen fluoride gas and nitric acid gas; bringing an exposed surface of the silicon wafer, exposed by the etching, into contact with gas generated from a mixed acid including hydrochloric acid and nitric acid; heating the silicon wafer that has been brought into contact with the gas generated from the mixed acid; bringing the exposed surface, exposed by the etching, of the silicon wafer after the heating into contact with a recovery solution; and analyzing a metal component in the recovery solution that has been brought into contact with the exposed surface, exposed by the etching, of the silicon wafer.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: July 28, 2020
    Assignee: SUMCO CORPORATION
    Inventor: Taisuke Mizuno
  • Patent number: 10699912
    Abstract: A computer program product and methods are provided for semiconductor processing. The method includes forming a masking layer on a first region. The method also includes implanting a second region. The method further includes depositing a protective layer over the first region and the second region, with the protective layer being selectively etchable to the masking layer and thicker over the second region. The additional includes removing the protective layer from the first region. The method also includes etching the masking layer exposing a bottom layer. The method further includes removing the protective layer from the second region and the bottom layer from the first region.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Indira Seshadri, Ekmini A. De Silva
  • Patent number: 10696869
    Abstract: A polishing composition capable of suppressing surface defects and reducing haze is provided. The polishing composition includes: abrasives; at least one water-soluble polymer selected from vinyl alcohol-based resins having a 1,2-diol structural unit; a polyalcohol; and an alkali compound. Preferably, the polishing composition further includes a non-ionic surfactant.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: June 30, 2020
    Assignee: NITTA HAAS INCORPORATED
    Inventors: Noriaki Sugita, Shuhei Matsuda, Takayuki Matsushita, Mika Tazuru
  • Patent number: 10685849
    Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: June 16, 2020
    Assignee: Applied Materials, Inc.
    Inventors: He Ren, Jong Mun Kim, Maximillian Clemons, Minrui Yu, Mehul Naik, Chentsau Ying
  • Patent number: 10685816
    Abstract: A method MT includes etching a wafer W using plasma generated in a processing container. The etching includes a process of inclining and rotating a holding structure holding the wafer W during execution of the etching and the process successively creating a plurality of inclined rotation states RT(?, t) with respect to the holding structure. In the inclined rotation states, the wafer W is rotated about a central axis of the wafer W over a predetermined process time while maintaining a state where the central axis is inclined with respect to a reference axis of the processing container which is in the same plane as the central axis. A combination of a value ? of an inclination angle AN of the central axis with respect to the reference axis and the process time t differs for each of the plurality of inclined rotation states.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: June 16, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihiro Umezawa, Jun Sato, Kiyoshi Maeda, Mitsunori Ohata, Kazuya Matsumoto
  • Patent number: 10676647
    Abstract: A chemical mechanical polishing composition includes a water based liquid carrier, cationic abrasive particles dispersed in the liquid carrier, a first amino acid compound having an isoelectric point of less than 7 and a second amino acid compound having an isoelectric point of greater than 7. The pH of the composition is in a range from about 1 to about 5. A method for chemical mechanical polishing a substrate including a tungsten layer includes contacting the substrate with the above described polishing composition, moving the polishing composition relative to the substrate, and abrading the substrate to remove a portion of the tungsten from the substrate and thereby polish the substrate.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: June 9, 2020
    Assignee: Cabot Microelectronics Corporation
    Inventors: Na Zhang, Kevin P. Dockery, Zhao Liu, Roman A. Ivanov
  • Patent number: 10670806
    Abstract: Method for preparing micro-optical structure on a film based on chemical mechanical polishing etching, combining photolithography technology with chemical mechanical polishing technology to make preparation and large-scale integration of large-size high-quality micro optical devices on-chip possible. The method comprises coating metal on film surface, selectively removing the metal film by photolithography (such as femtosecond laser selective ablation, ultraviolet photolithography, electron beam etching, ion beam etching, and reactive ion etching), chemical mechanical polishing, chemical corrosion or over polishing and other steps. Micro-optical devices on-chip prepared by the method have extremely high surface finish and extremely low optical loss.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: June 2, 2020
    Assignee: Shanghai Institute of Optics And Fine Mechanics, Chinese Academy of Sciences
    Inventors: Ya Cheng, Rongbo Wu, Jintian Lin, Jianhao Zhang, Min Wang
  • Patent number: 10672621
    Abstract: The pattern forming material of an embodiment is a pattern forming material containing a polymer composed of two or more kinds of monomer units, in which a first monomer unit in the monomer units is provided with an ester skeleton having a first carbonyl group and one or more second carbonyl groups which bind to the ester skeleton, among the second carbonyl groups, the second carbonyl group that is farthest from a main chain of the polymer constituting the pattern forming material is present on a linear chain, and a second monomer unit in the monomer units is provided with a crosslinkable functional group on a side chain terminal.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: June 2, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Norikatsu Sasao, Koji Asakawa, Tomoaki Sawabe, Shinobu Sugimura
  • Patent number: 10672617
    Abstract: There is provided an etching method which includes supplying an etching gas including an H2 gas or an NH3 gas to a target substrate having a germanium portion in an excited state; and etching the germanium portion.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 2, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroki Murakami, Takahiro Miyahara
  • Patent number: 10662533
    Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 26, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Tom E. Blomberg, Varun Sharma, Suvi P. Haukka, Marko J. Tuominen, Chiyu Zhu
  • Patent number: 10665425
    Abstract: Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 26, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Tom E. Blomberg, Varun Sharma, Suvi P. Haukka, Marko J. Tuominen, Chiyu Zhu
  • Patent number: 10662534
    Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 26, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Tom E. Blomberg, Varun Sharma, Suvi Haukka, Marko Tuominen, Chiyu Zhu
  • Patent number: 10665470
    Abstract: There is provided an etching method which includes: forming a blocking film configured to prevent an etching gas for etching a silicon-containing film from passing through each pore of a porous film and prevent the etching gas from being supplied to a film not to be etched, by supplying at least one film-forming gas to a substrate in which the silicon-containing film, the porous film, and the film not to be etched are sequentially formed adjacent to each other in a lateral direction; and etching the silicon-containing film by supplying the etching gas.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: May 26, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yasuo Asada, Takehiko Orii, Shinji Irie, Nobuhiro Takahashi, Ayano Hagiwara, Tatsuya Yamaguchi
  • Patent number: 10665480
    Abstract: A method for planarizing a workpiece includes bringing a surface of the workpiece and a surface of a pad having a catalyst layer at least on the surface thereof into contact with or proximal to each other, rotating a first one of the workpiece and the pad in a plane of the surface of the first one around a central axis that intersects the surface of the first one while supplying a liquid that supports a catalytic reaction between the surface of the workpiece and the catalyst layer on the surface of the pad, and simultaneously reciprocally moving a second one of the workpiece and the pad in a direction parallel to the surface of the second one by at least an amount that makes possible planarization of the surface of the workpiece based on the catalytic reaction.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 26, 2020
    Assignees: OSAKA UNIVERSITY, TOHO ENGINEERING CO., LTD.
    Inventors: Eisuke Suzuki, Kazuto Yamauchi, Tatsutoshi Suzuki, Daisuke Suzuki
  • Patent number: 10648087
    Abstract: Disclosed are processes of removing layers from substrates using fluorinated reactants having the formula MFx(adduct)n, wherein x ranges from 2 to 6 inclusive; n ranges from 0 to 5 inclusive; M is selected from the group consisting of P, Ti, Zr, Hf, V, Nb, Ta, Mo, and W; and the adduct is a neutral organic molecule selected from THF, dimethylether, diethylether, glyme, diglyme, triglyme, polyglyme, dimethylsulphide, diethylsulphide, or methylcyanide. The fluorinated reactants dry etch the nitride layers without utilizing any plasma.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 12, 2020
    Assignee: L'Air Liquide, SociétéAnonyme pour l'Exploitation et l'Etude des Procédés Georges Claude
    Inventors: Clément Lansalot-Matras, Jooho Lee, Jean-Marc Girard, Nicolas Blasco, Satoko Gatineau
  • Patent number: 10651048
    Abstract: A fabrication process employing the use of ScAlN as an etch mask is disclosed. The ScAlN etch mask is chemically nonvolatile in fluorine-based etch chemistries and has a low sputter yield, resulting in greater etch mask selectivity and reduced surface roughness for silicon and other semiconductor materials. The ScAlN etch mask has an etch mask selectivity of greater than 200,000:1 relative to silicon compared to an etch mask selectivity of less than 40,000:1 for a prior art AlN etch mask relative to silicon. Further, due to reduced sputtering of the ScAlN etch mask, and thus reduced micromasking, the ScAlN etch mask yielded a surface roughness of 0.6 ?m compared to a surface roughness of 2.8 ?m for an AlN etch mask.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: May 12, 2020
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Michael David Henry, Travis Ryan Young, Erica Ann Douglas
  • Patent number: 10639766
    Abstract: Described are materials and methods for processing (polishing or planarizing) a substrate that contains pattern dielectric material using a polishing composition (aka “slurry”) and an abrasive pad, e.g., CMP processing.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: May 5, 2020
    Assignee: Cabot Microelectronics Corporation
    Inventors: Viet Lam, Ji Cui
  • Patent number: 10640682
    Abstract: A process for chemical mechanical polishing a substrate containing tungsten is disclosed to reduce static corrosion rate and inhibit dishing of the tungsten and erosion of underlying dielectrics. The process includes providing a substrate; providing a polishing composition, containing, as initial components: water; an oxidizing agent; guar gum; a dicarboxylic acid, a source of iron ions; a colloidal silica abrasive; and, optionally a pH adjusting agent; providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the tungsten (W) is polished away from the substrate, static corrosion rate is reduced, dishing of the tungsten (W) is inhibited as well as erosion of dielectrics underlying the tungsten (W).
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: May 5, 2020
    Assignee: Rohm and Haas Electronics Materials CMP Holdings, Inc.
    Inventors: Wei-Wen Tsai, Lin-Chen Ho, Cheng-Ping Lee
  • Patent number: 10633557
    Abstract: A process for chemical mechanical polishing a substrate containing tungsten to reduce static corrosion rate and inhibit dishing of the tungsten and erosion of underlying dielectrics is disclosed. The process includes providing a substrate; providing a polishing composition, containing, as initial components: water; an oxidizing agent; xanthan gum; a dicarboxylic acid, a source of iron ions; a colloidal silica abrasive; and, optionally a pH adjusting agent; optionally a surfactant; providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the tungsten (W) is polished away from the substrate, static corrosion rate is reduced, dishing of the tungsten (W) is inhibited as well as erosion of dielectrics underlying the tungsten (W).
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 28, 2020
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Lin-Chen Ho, Wei-Wen Tsai, Cheng-Ping Lee
  • Patent number: 10633558
    Abstract: A process for chemical mechanical polishing a substrate containing tungsten is disclosed to reduce static corrosion rate and inhibit dishing of the tungsten and erosion of underlying dielectrics. The process includes providing a substrate; providing a polishing composition, containing, as initial components: water; an oxidizing agent; alginate; a dicarboxylic acid, a source of iron ions; a colloidal silica abrasive; and, optionally a pH adjusting agent; providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the tungsten (W) is polished away from the substrate, static corrosion rate is reduced, dishing of the tungsten (W) is inhibited as well as erosion of dielectrics underlying the tungsten (W).
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 28, 2020
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Wei-Wen Tsai, Lin-Chen Ho, Cheng-Ping Lee