Abstract: An etching method includes: providing, to an interior of a chamber, a substrate having a three-layered film formed by stacking a first silicon oxide-based film, a silicon nitride-based film, and a second silicon oxide-based film; and collectively etching the three-layered film using a HF—NH3-based gas in the interior of the chamber while adjusting a gas ratio in each of the first silicon oxide-based film, the silicon nitride-based film, and the second silicon oxide-based film.

Abstract: A method of generating chip-specific identification code marks on semiconductor chips includes patterning a resist layer over a semiconductor wafer by laser direct image exposure, the patterning including writing chip-specific identification codes into the resist layer over chip areas of the semiconductor wafer. The patterned resist layer is then developed.

Abstract: A recess filling method includes a combined process including a film formation process of forming a film in recesses formed on the surface of a substrate and having different aspect ratios, and an etching process of etching the film formed in the recesses; and a repetition process of repeating the combined process n times (n is a natural number of 2 or more), wherein the repetition process includes: a first combined process of performing the etching process with a first etching amount suitable for filling, with the film, a first recess having a first aspect ratio; and a second combined process of performing the etching process with a second etching amount that is smaller than the first etching amount and is suitable for filling, with the film, a second recess having a second aspect ratio lower than the first aspect ratio.

Abstract: Chemically treating ionically conductive sulfide glass solid electrolyte separators or separator layers can improve performance. In particular, treatment involving chemically etching a surface or surface region of the sulfide glass separator to blunt, lessen or remove edge defects or surface flaws, and/or to enhance surface smoothness is cost effective, reliable and well suited for high production environments compared to physical methods of removing scratches or smoothing surfaces, such as mechanical grinding and polishing.

Abstract: Provided are a polycrystalline SiC compact capable of achieving uniform plasma etching when used as electrodes and a method for manufacturing the same. A polycrystalline SiC compact has a major surface in which Wa (0 to 10 mm) is 0.00 to 0.05 ?m or less, Wa (10 to 20 mm) is 0.13 ?m or less, and Wa (20 to 30 mm) is 0.20 ?m or less.

Abstract: A method of etching a substrate includes loading the substrate into a plasma etch chamber, the plasma etch chamber including a focus ring surrounding the substrate, the focus ring including a bulk material and a surface layer, the surface layer including a refractory metal; flowing a process gas including fluorine and carbon into the plasma etch chamber; coating a carbide layer over the surface layer of the focus ring, the coating including exposing the focus ring to a plasma generated from the process gas in the plasma etch chamber, the carbide layer including a carbide of the refractory metal; and etching the substrate, the etching including exposing the substrate to the plasma.

Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

Abstract: A method of forming a semiconductor device may include forming a plurality of fins extending from a buried oxide layer, wherein a masking layer is disposed atop each of the plurality of fins, and performing a high-temperature ion implant to the semiconductor device. The method may further include performing an etch process to remove the masking layer from atop each of the plurality of fins, wherein the etch process does not remove the buried oxide layer.

Abstract: A substrate processing apparatus includes a chamber; a substrate support disposed in the chamber; a gas supply that supplies a gas into the chamber; and a controller that controls an overall operation of the substrate processing apparatus. The controller executes a process including: (a) placing a substrate on the substrate support, the substrate including an etching layer and a patterned mask on the etching layer; (b) forming a film on the patterned mask; (c) forming a reaction layer on the film; and (d) removing the reaction layer by applying energy to the reaction layer. In the step (c) a temperature of the substrate is set according to a thickness of the reaction layer to be formed.

Abstract: An etching gas mixture includes a nitrogen-containing compound and an inert gas. To manufacture an integrated circuit (IC) device, a silicon-containing film on a substrate is etched by using plasma generated from the etching gas mixture, and thus a hole is formed in the silicon-containing film. The nitrogen-containing compound is selected from a compound represented by Formula 1 and a compound represented by Formula 2: (R1)C?N ??[Formula 1] wherein in Formula 1, R1 is a C2 to C3 linear or branched perfluoroalkyl group, (R2)(R3)C?NH ??[Formula 2] wherein in Formula 2, each of R2 and R3 is independently a C1 to C2 linear perfluoroalkyl group.

Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Abstract: This disclosure relates to polishing compositions that include (1) at least one abrasive; (2) at least one organic acid or a salt thereof; (3) at least one first amine compound, the at least one first amine compound including an alkylamine having a 6-24 carbon alkyl chain; (4) at least one second amine compound containing at least two nitrogen atoms, the second amine compound being different from the first amine compound; and (5) an aqueous solvent.

Abstract: The current disclosure relates to methods of selectively etching material from a first surface of a substrate relative to a second surface of the substrate. The method includes providing the substrate having a first surface comprising an etchable material, and a second surface comprising a non-etchable material in a reaction chamber, providing hydrogen-containing plasma into the reaction chamber to reduce the etchable material to a predetermined depth; and providing remotely-generated reactive halogen species and hydrogen into the reaction chamber to selectively etch the reduced etchable material. The disclosure further relates to methods of selectively etching at least two different etchable materials simultaneously from a surface of a substrate relative to a non-etchable material on the same substrate, to methods of simultaneous differential etching of three or more etchable materials on a substrate, as well as to assemblies for processing semiconductor substrates.

Abstract: A method of forming a semiconductor device includes forming a mask layer over a substrate and forming an opening in the mask layer. A gap-filling material is deposited in the opening. A plasma treatment is performed on the gap-filling material. The height of the gap-filling material is reduced. The mask layer is removed. The substrate is patterned using the gap-filling material as a mask.

Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.

Abstract: A method of processing a substrate that includes: loading the substrate in a plasma processing chamber, the substrate including an underlying layer; maintaining a steady state flow of a process gas into the plasma processing chamber in the plasma processing chamber; generating a plasma in the plasma processing chamber; exposing the substrate to the plasma to etch the underlying layer; and pulsing a first additional gas, using a first effusive gas injector, towards a first region of the substrate to disrupt the steady state flow of the process gas over the first region, the pulsing locally changing a composition of the plasma near the first region.

Abstract: A method for producing a nanoscale channel structure disclosed. The method includes depositing and structuring a first sacrificial layer on a substrate, depositing a second sacrificial layer on the substrate and on the first sacrificial layer, depositing an etching masking layer on the second sacrificial layer, partly removing the etching masking layer and the second sacrificial layer, removing the first sacrificial layer and additionally partly removing the second sacrificial layer, depositing a wall layer on the etching masking layer and on the substrate, structuring access openings to the second sacrificial layer, and removing the remaining second sacrificial layer.

Abstract: Patterned magnetoresistive random access memory (MRAM) stacks are formed by performing a main etch through a plurality of MRAM layers disposed on a substrate, where the main etch includes using ion beam etching (IBE). After the main etch, gapfill dielectric material is deposited in spaces between the patterned MRAM stacks, and the gapfill dielectric material is selectively etched or otherwise formed to an etch depth that is above a depth of an underlayer. After the gapfill dielectric material is formed, at least some of the gapfill dielectric material and any electrically conductive materials deposited on sidewalls of the patterned MRAM stacks are removed by performing an IBE trim etch.

Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl2 and BCl3.

Abstract: Patterning electronic devices using reactive-ion etching of tin oxides is provided. Reactive-ion etching facilitates patterning of tin oxides, such as barium stannate (BaSnO3), at a consistent and controllable etch rate. The reactive-ion etching approach described herein facilitates photolithographic patterning of tin oxide-based semiconductors to produce electronic devices, such as thin-film transistors (TFTs). This approach further patterns a tin oxide-based semiconductor without adversely affecting its electrical properties (e.g., resistivity, electron or hole mobility), as well as maintaining surface roughness. This approach can be used to produce optically transparent devices with high drain current (ID, drain-to-source current per channel width) and high on-off ratio.