Abstract: A method for processing a transparent workpiece includes directing a pulsed laser beam into the transparent workpiece such that a portion of the pulsed laser beam directed into the transparent workpiece generates an induced absorption within the transparent workpiece, thereby forming a damage line within the transparent workpiece, and the portion of the pulsed laser beam directed into the transparent workpiece includes a wavelength ?, a spot size w0, and a Rayleigh range ZR that is greater than F D ? ? ? w 0 2 ? , where FD is a dimensionless divergence factor comprising a value of 10 or greater. Further, the method for processing the transparent workpiece includes etching the transparent workpiece with an etching vapor to remove at least a portion of the transparent workpiece along the damage line, thereby forming an aperture extending through the at least a portion of the thickness of the transparent workpiece.

Abstract: There is provided a wafer processing method for reducing a thickness of a wafer. The wafer has a front side and a back side opposite to the front side. The wafer has a device area where a plurality of devices are formed on the front side and a peripheral marginal area including a curved peripheral edge. A protective layer for covering the plural devices are formed on the front side in the device area. The wafer processing method includes a plasma etching step of supplying an etching gas in a plasma condition to the front side of the wafer by using the protective layer as a mask, thereby removing the peripheral marginal area including the curved peripheral edge, a protective member attaching step of attaching a protective member to the front side of the wafer, and a grinding step of grinding the back side of the wafer.

Abstract: Processing methods may be performed to form semiconductor structures that may include three-dimensional memory structures. The methods may include forming a plasma of a fluorine-containing precursor in a remote plasma region of a processing chamber. The methods may include contacting a semiconductor substrate with effluents of the plasma. The semiconductor substrate may be housed in a processing region of the processing chamber. The methods may include selectively cleaning exposed nitride materials with the effluents of the plasma. The methods may also include subsequently depositing a cap material over the cleaned nitride material. The cap material may be selectively deposited on the nitride material relative to exposed regions of a dielectric material.

Abstract: This mask blank has a structure wherein a phase shift film and a light shielding film are sequentially formed as layers in this order on a transparent substrate. The optical density of the layered structure composed of the phase shift film and the light shielding film with respect to exposure light, which is an ArF excimer laser, is 3.5 or more; and the light shielding film has a structure wherein a lower layer and an upper layer are formed as layers sequentially from the transparent substrate side. The lower layer is formed from a material wherein the total content of chromium, oxygen, nitrogen and carbon is 90 atomic % or more; and the upper layer is formed from a material wherein the total content of metals and silicon is 80 atomic % or more. The extinction coefficient kU of the upper layer for the exposure light is higher than the extinction coefficient kL of the lower layer for the exposure light.

Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method for processing a substrate includes applying at least one of low frequency RF power or DC power to an upper electrode formed from a high secondary electron emission coefficient material disposed adjacent to a process volume; generating a plasma comprising ions in the process volume; bombarding the upper electrode with the ions to cause the upper electrode to emit electrons and form an electron beam; and applying a bias power comprising at least one of low frequency RF power or high frequency RF power to a lower electrode disposed in the process volume to accelerate electrons of the electron beam toward the lower electrode.

Abstract: The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material over an underlying layer. The spacer material has sidewalls defining a first trench. A cut material is formed over the spacer material and within the first trench. The cut material separates the trench into a pair of trench segments having ends separated by the cut material. The underlying layer is patterned according to the spacer material and the cut material.

Abstract: A method for opening an amorphous carbon layer mask below a hardmask is provided. The opening an amorphous carbon layer mask comprises performing one or more cycles, where each cycle comprises an amorphous carbon layer mask opening phase and a cleaning phase. The amorphous carbon layer mask opening phase comprises flowing an opening gas into a plasma processing chamber, wherein the opening gas comprises an oxygen containing component, creating a plasma from the opening gas, which etches features in the amorphous carbon layer mask, and stopping the flow of the opening gas. The cleaning phase comprises flowing a cleaning gas into the plasma processing chamber, wherein the cleaning gas comprises a hydrogen containing component, a carbon containing component, and a halogen containing component, creating a plasma from the cleaning gas; and stopping the flow of the cleaning gas into the plasma processing chamber.

Abstract: Polishing compositions that can selectively and preferentially polish certain dielectric films over other dielectric films are provided herein. These polishing compositions include either cationic or anionic abrasives based on the target dielectric film to be removed and preserved. The polishing compositions utilize a novel electrostatic charge based design, where based on the charge of the abrasives and their electrostatic interaction (forces of attraction or repulsion) with the charge on the dielectric film, various material removal rates and polishing selectivities can be achieved.

Abstract: At least one embodiment relates to a method fabricating a solid-state battery cell. The method includes forming a plurality of spaced electrically conductive structures on a substrate. Forming the plurality of spaced electrically conductive structures on the substrate includes transforming at least part of a valve metal layer into a template that includes a plurality of spaced channels aligned longitudinally along a first direction. Transforming at least part of the valve metal layer into the template includes a first anodization step, a second anodization step, an etching step in an etching solution, and a deposition step. The method also includes forming a first layer of active electrode material on the plurality of spaced electrically conductive structures, depositing an electrolyte layer over the first layer of active electrode material, and forming a second layer of active electrode material over the electrolyte later.

Abstract: Provided is a mask blank for a phase shift mask including an etching stopper film. A mask blank has a structure where a transparent substrate has layered thereon an etching stopper film and a phase shift film in this order, in which the phase shift film contains silicon and oxygen, in which the phase shift film has a refractive index n1 of 1.5 or more for light of 193 nm wavelength and an extinction coefficient k1 of 0.1 or less for light of 193 nm wavelength, in which the etching stopper film has a refractive index n2 of 2.6 or more for light of 193 nm wavelength and an extinction coefficient k2 of 0.4 or less for light of 193 nm wavelength, and the refractive index n2 and the extinction coefficient k2 satisfy at least one of k2?[(?0.188×n2)+0.879] and k2?[(2.75×n2)?6.945].

Abstract: According to one embodiment, a pattern forming method includes forming an organic layer on a first layer. The organic layer has a first region having a first thickness and a first width, a second region having a second thickness and a second width, and a third region located between the first region and the second region. The third region has a third thickness less than each of the first thickness and the second thickness and a third width. A second layer containing silicon oxide is then formed on a surface of the organic layer in a process chamber of a reactive ion etching device. The third region is then etched in the process chamber using the second layer as a mask.

Abstract: A method of manufacturing a ceramic electronic component includes forming a dielectric layer including a plurality of ceramic nanosheets on a first electrode, treating the dielectric layer with an acid, and forming a second electrode on the dielectric layer, a ceramic electronic component, and an electronic device.

Abstract: A mask blank in which a phase shift film provided on a transparent substrate includes at least a nitrogen-containing layer and an oxygen-containing layer, the nitrogen-containing layer contains silicon and nitrogen and the oxygen-containing layer contains silicon and oxygen, wherein, when the nitrogen-containing layer is subjected to X-ray photoelectron spectroscopy to obtain a maximum peak PSi_f of photoelectron intensity of a Si2p narrow spectrum and the transparent substrate is subjected to X-ray photoelectron spectroscopy to obtain a maximum peak PSi_s of photoelectron intensity of a Si2p narrow spectrum, the numerical value (PSi_f)/(PSi_s), which is produced by dividing the maximum peak PSi_f in the nitrogen-containing layer by the maximum peak PSi_s in the transparent substrate, is 1.09 or less.

Abstract: Disclosed is a chemical-mechanical polishing slurry composition having a small change in pH over time under an acidic condition and thus being easy to store for a long time. The chemical-mechanical polishing slurry composition includes an abrasive; an amount of about 0.000006 to 0.01 weight % of an aluminum component based on the total weight of the polishing slurry composition; and water. The number of silanol groups on a surface of the abrasive and a content of the aluminum component satisfy the requirements of following Equation 1: 0.0005?(S*C)*100?4.5,??[Equation 1] wherein, S is the number of the silanol groups present on 1 nm2 of the abrasive surface (unit: number/nm2), and C is the content of the aluminum component (weight %) in the slurry composition.

Abstract: A polishing composition according to the present invention is used to polish an object to be polished including a high dielectric constant layer, in which the polishing composition contains an abrasive grain, water, and organic acid, when a zeta potential of the abrasive grain in the polishing composition is set as X [mV], and a zeta potential of the high dielectric constant layer during polishing using the polishing composition is set as Y [mV], X is positive, and Y?X??5 is established.

Abstract: A dry etching process for manufacturing a trench structure of a semiconductor apparatus, including the steps of: step 1, providing a semiconductor substrate, wherein the semiconductor substrate is provided with a patterned photoresist layer and placed in a reaction chamber; step 2, introducing a first etching gas into the reaction chamber to perform a first etching process to form a trench, wherein the first etching gas includes sulfur hexafluoride, oxygen, helium, nitrogen trifluoride, and a first organic silicide; step 3, introducing a second etching gas into the reaction chamber to perform a second etching process to further etch the trench, wherein the second etching gas includes sulfur hexafluoride, oxygen, helium, and a second organic silicide; and step 4, introducing a third etching gas into the reaction chamber to perform a third etching process, wherein the third etching gas includes hydrobromic acid, oxygen, and helium.

Abstract: A method for manufacturing a semiconductor device according to an embodiment includes: forming a first layer on a semiconductor substrate, a surface of the first layer having a first plane of which distance from the semiconductor substrate is a first distance and a second plane of which distance from the semiconductor substrate is a second distance smaller than the first distance, and a difference between the first distance and the second distance being 30 nm or more; performing planarization processing on the first layer to have the difference of less than 30 nm; forming a second layer directly on the first layer after performing the planarization processing; supplying a resist to the second layer; bringing a template having a pattern into contact with the resist to form a resist layer to which the pattern has been transferred; and etching the second layer using the resist layer as a mask.

Abstract: Methods to improve front-side process uniformity by back-side metallization are disclosed. In some implementations, a metal layer is deposited on the back-side of a wafer prior to performing a plasma-based process on the front side of the wafer. Presence of the back-side metal layer reduces variations in, for example, thickness of a deposited and/or etched layer resulting from the plasma-based process.

Abstract: A method of patterning a substrate includes receiving a substrate having microfabricated structures, including mandrels; executing a deposition process that deposits a first material on the mandrels, the deposition process including cyclically moving the substrate through a set of deposition modules. The substrate is moved through the set of deposition modules so that the first material is deposited at a first thickness at top portions of the mandrels and at a second thickness at bottom portions of mandrels, the first thickness being greater than the second thickness. The method includes executing a spacer deposition process that conformally deposits a second material on the substrate; executing a spacer open etch that removes depositions of the second material from over a top surface of the mandrels; removing the first material and the mandrels from the substrate, leaving sidewall spacers; and transferring a pattern defined by the sidewall spacers into an underlying layer.

Abstract: There is provided a new and improved master manufacturing method, master, and optical body enabling more consistent production of optical bodies having a desired haze value, the master manufacturing method including: forming a first micro concave-convex structure, in which an average cycle of concavities and convexities is less than or equal to visible light wavelengths, on a surface of a base material body that includes at least a base material; forming an inorganic resist layer on the first micro concave-convex structure; forming, on the inorganic resist layer, an organic resist layer including an organic resist and filler particles distributed throughout the organic resist; and etching the organic resist layer and the inorganic resist layer to thereby superimpose and form on the surface of the base material a macro concave-convex structure and a second micro concave-convex structure.