Abstract: A low height disk drive having an overall height of approximately one inch (1"). The drive includes a head disk assembly, including a base plate, a disk rotatably supported on the base plate, a motor for rotating the disk, at least one head for reading information from and writing information on the disk, an actuator, supported on said base plate and responsive to control signals, for selectively positioning the head with respect to the disk, and a cover sealably attached to the base plate to enclose the storage means, the head, and the actuator. The disk drive also includes control circuitry for generating control signals, and for providing information signals to and receiving information signals from the head. The head disk assembly and the control circuitry have a combined height of approximately one inch or less.
Abstract: A circuit and method for depuncturing data in the receiver circuitry of a digital communications system. The depuncturing circuit includes a multiplexer circuit that receives a punctured stream of data and a delayed version of the punctured stream of data. The multiplexer circuit generates a multiplexer output which can be either a bit from the punctured stream of data, or a bit from the delayed version of the punctured stream of data. A control circuit is coupled to the multiplexer circuit to select which multiplexer input appears on the multiplexer output. The control circuit selects the multiplexer output according to a depuncture pattern that reproduces the pre-punctured order of the data stream. The control circuit may be a counter coupled to a decoder which is coupled to the multiplexer. The decoder may be specially designed to decode the predetermined depuncture pattern and rate, and the counter controls the decoder's movement through the depuncture pattern and rate.
Abstract: Data on the outline of an applique to be cut out and embroidered are inputted by a digitizer, etc. to a microcomputer only once. Data for cutting out the applique and data for embroidering it are both prepared from the inputted outline data for delivery to a cutting device and an embroidering machine, respectively.
Abstract: In a video cassette recorder incorporating two interconnected microcomputers for its control, an automatic watchdog method sends from a first microcomputer a request command for watchdog data to a second microcomputer periodically. Upon receiving the watchdog data request command, the second microcomputer, if operating normally, is forced to respond to the watchdog data generated in a predetermined manner. Accordingly, when the first microcomputer receives the watchdog data generated not in the predetermined manner, or does not receive the watchdog data at all, it recognizes that the second microcomputer is in an errant state. When the first microcomputer detects such an abnormality in the second microcomputer, it reinitializes the second microcomputer through a reset port thereof.
Abstract: A storage controller operates an array of parity protected data storage units as a RAID level 5. One of the storage units is a dedicated write assist unit. The assist unit is a temporary storage area for data to be written to the other units. When the array controller receives data from a host, it first writes the data to the assist unit. Because the assist unit is not parity protected and is only temporary storage, it is possible to write data to the assist unit sequentially, without first reading the data, greatly reducing response time. The array controller signals the CPU that the data has been written to storage as soon as it has been written to the assist unit. Parity in the array is updated asynchronously. In the event of system or storage unit failure, data can be recovered using the remaining storage units and/or the assist unit. The write assist unit also doubles as a spare unit.
May 6, 1992
Date of Patent:
January 13, 1998
International Business Machines Corporation
Abstract: A virtual reality generator having an input module that receives as input financial information is disclosed. The virtual reality generator outputs to a display device a virtual reality world generated from the financial information. The financial information can be pre-processed by a financial analytic system prior to input to the virtual reality generator. The financial information can be received from a data file. The virtual reality generator can dynamically display and continuously update the virtual reality world. Further, movement through the virtual reality world can be simulated.
Abstract: Low-frequency components of a reproduced modulated signal is attenuated by an analog high-pass filter. The modulated signal with its low-frequency components attenuated is converted into a digital signal by means of an A/D converter. Then, the digital signal is directly introduced to a finite impulse response digital filter to be subjected to reproduced waveform equalization. Thereafter, the attenuation of the low-frequency components effected by the analog high-pass filter is compensated in an infinite impulse response digital filter.
Abstract: Rounding error can be reduced when evaluating binary floating point polynomials utilizing a Floating Point Unit (58) by first computing the sum of products of second and higher order polynomial terms. Next, the Floating Point Unit (58) adds a zero.sup.th level term to the product of a first order coefficient and an independent variable to form a "Big" term. The Floating Point Unit (58) calculates as a "Little" term the rounding error resulting from the computation of the "Big" term. The "Little" term is then added to the sum of products of higher order terms to form an "Intermediate" term. Finally, the Floating Point Unit (58) adds the "Big" term to the "Intermediate" term to form the polynomial result corrected by the rounding error introduced by the computation of the low order terms.
Abstract: A circuit and method includes a global parity symbol in a multi-way interleaved Reed-Solomon code implementation to enhance error-detection capability of the Reed-Solomon code. In one embodiment, the global parity symbol is computed over both the data symbols and the check symbols of the Reed-Solomon code, thereby providing data detection capability for errors occurring in the check symbols.
July 5, 1994
Date of Patent:
June 24, 1997
Frank S. Lee, David H. Miller, Richard W. Koralek
Abstract: A disk apparatus wherein a disk is rotated by a rotating motor, and a source power supplied to the rotating motor is monitored, which includes: a memory unit for storing an initial source voltage value before a process of a rotating motor acceleration is started; a detecting unit for periodically detecting a source voltage value related to the source power; a comparing unit for comparing the source voltage value, detected by the detecting unit during the process of the rotating motor acceleration, with the initial source voltage value stored in the memory unit, and for outputting a voltage fluctuation indicated by a difference between the source voltage value and the initial source voltage value; and a control unit for setting a quantity of the source power supplied to the rotating motor, to a smaller quantity in response to the voltage fluctuation output by the comparing unit.
Abstract: A time-discrete signal is delayed by a selectable fraction (.delta.) of a sampling period of the time-discrete signal. First (F1) and second (F2) differential signals having mutually different phase characteristics are derived from the time-discrete signal and are subsequently combined (MIX) dependent upon the selectable fraction (.delta.) to obtain a phase-adjusted correction signal. The product of the selectable fraction (.delta.) and the correction signal is added to the time-discrete signal to obtain a time-discrete signal which has been delayed by the selectable fraction (.delta.). The second differential signal is obtained by means of a differentiator with asymmetric coefficients in order to optimise the transfer characteristic for .delta.=0.5.
Abstract: An apparatus for feedback adjusting the working condition of a working machine on the basis of measured dimensions of processed workpieces, including a determining device for determining automatic and manual compensating values, and an applying device for applying the automatic and manual compensating values (Ui, U') to a machine controller for adjusting the machine working condition. The determining device determines the automatic compensating value on the basis of first or second estimated dimensional values of the workpieces obtained in an automatic compensating cycle. Each first estimated dimensional value is a sum of an actually measured dimension (X) of the workpiece and a last compensating value (U'), while each second estimated dimensional value is a sum of the actually measured dimension, the last compensating value and a previous compensating value (Ui-2, Ui-1) preceding the last compensating value. Also disclosed is a method of feedback adjusting the machine working condition.
Abstract: A method and apparatus for multi-channel control of a multiple input, multiple output, servo-driven plant utilizes finite impulse response (FIR) filters to model the inverse of the plant. Each channel includes a servo FIR filter that generates a servo command to drive the plant's servo controller, a valve current FIR filter that bypasses the PID stage of the servo controller to avoid undesirable effects of the PID loop, and a cross FIR filter for each of the remaining channels that compensates for physical coupling in the plant between the channels. The servo FIR filter is calculated by an adaption routine that involves applying an identification signal to the plant, applying the plant's response to the filter and then updating the filter's coefficients using the error that exists between the identification signal and the filter output.
Abstract: A computer system is provided which has ECC, and which system has a first group of SIMMs having DRAMs thereon for storing data bits and a second group of SIMMs having DRAMs thereon for the storage of check bits. The system also has a memory controller which is programmed to operate at least about 10 nanoseconds slower than the DRAMs. During the write cycle, check bits are generated for and specific to each data byte, with the bits of the data byte being stored in the first group of SIMMs and the check bits stored in the second group of SIMMs. During the read cycle, new check bits are generated and compared with the stored check bits. Each single bit error is corrected and certain multiple bit errors are detected.
December 15, 1994
Date of Patent:
April 22, 1997
International Business Machines Corporation
Abstract: An apparatus for controlling real time processes is described. A timing chart desired input and output signals to control the real time processes is displayed on a display screen. The timing chart is converted to a set of instructions for monitoring the input signals and governing the output signals. A control, operative for controlling the real time process and responsive to the instructions, monitors the input signals and governs the output signals in real time.
Abstract: In a state where definition of machining has been already finished for the first to N-th processes, such data as a machining kind, tool data including a tool code, and cutting conditions related to the j-th process (1.ltoreq.j.ltoreq.N+1) are inputted as new data or modified data in an interactive mode on a screen. Next, a shape of the workpiece at a point of time when the (j-1)th machining process has been finished and the final shape of the workpiece to be cut are displayed on a screen, and a cutting area for the j-th machining process is set or modified by means of the screen. Then, a shape of the workpiece at a point of time when the j-th process is finished is found on the basis of the inputted data, and a cutting area to be newly cut or to be modified in the j-th machining process is identified and displayed by displaying one upon the other on the screen the found shape of the workpiece and a shape of the workpiece at a point of time when the (j-1)th process has been finished.
Abstract: A technique for efficiently utilizing memory in determining a next state accumulated cost in a communications system or a Viterbi decoder. The system includes a memory having an array of registers. A first present state accumulated cost is retrieved from a first storage register of the array. A second present state accumulated cost is retrieved from a second storage register of the array. A first next state accumulated cost is calculated based on the first present state accumulated cost. The first next state accumulated cost is stored in the first storage register of the array. An advantage of the invention is that such a technique requires less memory to calculate and store accumulated costs. The number of memory locations required is one for each individual state, which is substantially half of the memory locations required previously.
Abstract: A computer system replaces an input device, such as a mouse, with a video camera having an image recognizing function and an image extracting function to detect motions of the operator's body directly, and controls a computer apparatus to move a cursor and check on an icon on the basis of the output signals of the video camera. The computer system controls the computer apparatus also on the basis of a signal provided by the video camera upon the detection of light emitted by a particular object. The computer system is capable of making the computer apparatus understand an operator's intention without using any conventional input device, such as a mouse, and of facilitating an operator's input operation.
Abstract: A microcontroller capable of operating in any one of several operation modes and includes first latch circuits which latch first mode signals from first external nodes at a first timing and second latch circuits latching second mode signals from the same external nodes at a second timing. Operation modes are switched by using the mode signals stored in the first and second latch circuits, so that a single external node can provide two bits for expressing the operation modes. Thus, the number of bits used to represent the mode signal can be increased without increasing the number of external nodes. Also provided is a microcontroller in which the time required for a test can be reduced by eliminating the waiting period for clock generation to be stabilized.