Patents Examined by Roy N. Envall, Jr.
  • Patent number: 5604752
    Abstract: A decoder of a communication apparatus includes a CPU which controls decoding processing, and a memory which stores a decoding processing program. The decoding processing program includes a syndrome polynomial generating unit which generates a syndrome polynomial on the basis of a received word, a polynomial updating unit which updates an error locator polynomial and an error evaluator polynomial, which are set using the generated syndrome polynomial, on the basis of a degree of the error locator polynomial, and a decoded sequence generating unit which generates a decoded sequence on the basis of the error locator polynomial and the error evaluator polynomial, thus decoding communication codes at a high speed with a minimal computational complexity.
    Type: Grant
    Filed: December 27, 1994
    Date of Patent: February 18, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventor: Keiichi Iwamura
  • Patent number: 5604678
    Abstract: Elongated thin strip stock is blanked to form interlocking laminas for electric motor or generator rotors or stators at successive blanking stations. At a final assembly station the laminas are stacked and pressed into interlocking relationship. In response to an operator input a predetermined number of reversals, or half turns about the stack axis of the previously stacked lamina are provided in order to compensate for nonuniform strip thickness to obtain a rotor or stator of substantially uniform height. Alternatively the thickness of the strip stock is gauged at transversely spaced points on the strip to determine cross feed thickness variation in the strip whereupon the stacked laminas are automatically provided with a number of reversals about the stack axis in response to a thickness differential that would result in a parallelism error in the stack that exceeds a predetermined amount.
    Type: Grant
    Filed: July 25, 1994
    Date of Patent: February 18, 1997
    Assignee: L.H. Carbide Corporation
    Inventor: Thomas R. Neuenschwander
  • Patent number: 5602767
    Abstract: The multiply/divide circuit uses an exclusive OR function of an ALU in a DSP. The result of the exclusive OR function through accumulators and shift registers which recycle the shifted signals back to the ALU, can be made to perform the multiply or divide function. When used in a DSP for telecommunication purposes, the multiply/divide circuit can perform convolution encoding and cyclic redundancy check, among other functions, specifically for the telecommunication application.
    Type: Grant
    Filed: August 29, 1995
    Date of Patent: February 11, 1997
    Assignee: TCSI Corporation
    Inventors: Gerhard P. Fettweis, Mihran Touriguian
  • Patent number: 5602728
    Abstract: A three button programmable sprinkler control system includes a control module having an LCD display, a decrement button, an increment button, and a set or select button. In a preferred embodiment, the control module is battery powered, sized for hand holding, and conveniently positionable in and removable from a system cabinet having therein a power transformer and base triac board including a base set of zone valve triacs. The system cabinet is sized to receive an expansion board having a second group of triacs for expanding the number of sprinkler valves which can be controlled. The control module includes a processor having stored therein a control program which is menu based and which is accessed for setting irrigation control parameters by operation of the three switches with reference to icons displayed for the various menus. The control module interfaces with the base triac board and an expansion board by a connector.
    Type: Grant
    Filed: September 7, 1994
    Date of Patent: February 11, 1997
    Assignee: Watermation Group Ltd.
    Inventors: Peter R. Madden, Franciscus B. J. M. Beks, Graham J. Nutt, Robert A. Caviar
  • Patent number: 5602748
    Abstract: An area machining method capable of generating tool paths with no insufficient cut portion. First, a part profile contour indicating a profile contour for area machining and various machining conditions such as tool radius, depth of cut and the like are preset. Then the outmost offset contour and other subsequent offset contours are obtained, the outmost offset contour being offset along the part profile contour by an amount of the sum of a tool radius and finishing allowance, and the other subsequent offset contours being offset repeatedly from the outmost offset contour in sequence by an amount of depth of cut in the inside direction. Next, contours of insufficient cut portions which are produced between adjacent offset contours are obtained. Subsequently, tool paths each of which connects between offset contours and between an offset contour and a corresponding insufficient cut portion contour are outputted.
    Type: Grant
    Filed: January 24, 1995
    Date of Patent: February 11, 1997
    Assignee: FANUC Ltd.
    Inventors: Masaki Seki, Takashi Takegahara, Shigetoshi Takagi, Shinya Nakamura
  • Patent number: 5602746
    Abstract: It is the object of the invention to provide a printing method permitting a high printing quality and reducing the influences of the forces and fields acting on the printing material. The object is achieved in that, by means of two image-detecting arrangements disposed in the transport path of the printing material, image signals are obtained before and behind a device treating the surface of the printing material and are supplied to a control unit, and in that the changes of the outer dimensions are quantitatively determined on the basis of said image signals. The invention may be applied on printing machines.
    Type: Grant
    Filed: January 27, 1995
    Date of Patent: February 11, 1997
    Assignee: Heidelberger Druckmaschinen AG
    Inventor: Gerhard Loffler
  • Patent number: 5602769
    Abstract: A method for fully supporting floating point multiplication using a combination of partial hardware support and partial software support traps to software when a subnormal operand is encountered and gross underflow cannot be determined without determining the leading zeros in the subnormal mantissa. A simplified hardware multiplier does not require leading zero detection or left or right shifting. The partial hardware support circuit allows single and double precision operands. The hardware multiplier unit only partially supports subnormal operands. If one of the operands is subnormal, the hardware multiplier unit will output zero and a gross underflow signal if the multiplication would result in gross underflow. There is a small minority of operand permutations that are not supported in hardware and thus require a greater time to compute by resorting to software. However, the vast majority of operand permutations gain reduced latency.
    Type: Grant
    Filed: July 5, 1995
    Date of Patent: February 11, 1997
    Assignee: Sun Microsystems, Inc.
    Inventors: Robert K. Yu, Grzegorz B. Zyner
  • Patent number: 5600664
    Abstract: The information reproducing apparatus according to the present invention is the information reproducing apparatus which reproduces the data from the recording medium by utilizing the partial response system and decodes the data by using the shift register on the basis of the Viterbi decoding method, wherein the shift register includes the flip-flops Da.sub.j as the plurality of latch means connected in series for latching the data and the XOR gates 31a to 31d as the arithmetic means which are disposed between the adjacent flip-flops Da.sub.j to carry out CRC calculation and which calculates the exclusive-ORs of the outputs of the flip-flops Da.sub.j.
    Type: Grant
    Filed: November 1, 1994
    Date of Patent: February 4, 1997
    Assignee: Sony Corporation
    Inventor: Nobuhiro Hayashi
  • Patent number: 5600570
    Abstract: A method for modeling a synthetic crystal structure formed of a first crystal structure and a second crystal structure by representing the first crystal structure using a first coordinate system and the second crystal structure using a second coordinate system, specifying a first atom, a first lattice and a first crystal face of the first crystal structure, the first crystal face including the first atom and the first lattice; specifying a second atom, a second lattice and a second crystal face of the second crystal structure the second crystal face including the second atom and the second lattice; transforming the second crystal structure system represented by the second coordinate system into a second crystal structure represented by the first coordinate system so that an assembling condition is satisfied, the assembling condition being defined as a condition in which the second atom, the second lattice and the crystal face of the second crystal structure are respectively superposed on the first atom, the f
    Type: Grant
    Filed: March 6, 1992
    Date of Patent: February 4, 1997
    Assignee: Fujitsu Ltd.
    Inventors: Yutaka Imasato, Masahito Kawai
  • Patent number: 5600581
    Abstract: A converter which may be used for implementing either logarithmic or inverse-logarithmic functions includes a memory, a multiplier, and an adder. The memory stores a plurality of pre-computed values which are used in an interpolation to estimate a logarithmic or inverse-logarithmic function over a domain of input signals.
    Type: Grant
    Filed: February 22, 1995
    Date of Patent: February 4, 1997
    Assignee: Motorola, Inc.
    Inventors: James D. Dworkin, Philip B. Giangarra, Stephen L. Smith
  • Patent number: 5600584
    Abstract: A method for tracking errors in a system of numerical formulas. It uses confidence intervals and special encodings, and is suitable for use in an interactive computer program. Maximum efficiency and accuracy are attained by using directed rounding and compiling into native code.
    Type: Grant
    Filed: September 15, 1992
    Date of Patent: February 4, 1997
    Inventor: Roger Schlafly
  • Patent number: 5600565
    Abstract: Each item a system or order group carries a label having, in addition to a predetermined primary code denoting its item type, another, secondary, code representing a random identifier for that individual item. When a system or order group is to be packaged, a worker selects each item according to a list, scans its label, and physically places the item with the order group. The predetermined primary and random secondary codes are compared with those of previous items in the same order group. A complete match with the codes of another item in the same group causes the item to be rejected.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: February 4, 1997
    Assignee: International Business Machines Corporation
    Inventors: Steven L. Wagner, Stephen E. Wheeler
  • Patent number: 5600564
    Abstract: A coke oven communication and control system uses high frequency spread spectrum transceivers which are land based (connected to a central controller) and machine based (on a charging car, door machine, pusher, or quench car). Each land based transceiver communicates with a single corresponding machine based transceiver, there being different frequencies for each of the machines. Except for the quenching car transceivers, the other land and machine transceivers all are selectively connected to a pair of antennas which are alternately used to overcome interference. An advantageous communication technique is used to send data between a central controller, known as a battery programmable logic controller (PLC), and the machines. Control strategies are used to minimize malfunctioning of the coke oven battery.
    Type: Grant
    Filed: December 1, 1994
    Date of Patent: February 4, 1997
    Assignee: National Steel Corporation
    Inventors: James J. Tarasiewicz, Edward C. Nichols
  • Patent number: 5596589
    Abstract: A communication device (140) for receiving and decoding a codeword of predetermined length, wherein the codeword includes information and parity bits, comprises a memory (315) for storing the codeword in the form of segments, wherein each segment comprises multiple bits forming bit combinations. A first look-up table (326, 327, 328, 329) included in the communication device (140) stores parity vectors corresponding to the bit combinations, and a second look-up table (325) stores values corresponding to syndrome vectors. A processing unit (310) coupled to the memory (315) and the first and second look-up tables (325-329) uses the bit combinations of the segments as indices into the first look-up table (326-329) to locate corresponding parity vectors, adds the corresponding parity vectors using modulo 2 arithmetic to form a resulting syndrome, and uses the resulting syndrome as an index into the second look-up table (325) to locate an erroneous bit included in the codeword.
    Type: Grant
    Filed: October 29, 1993
    Date of Patent: January 21, 1997
    Assignee: Motorola, Inc.
    Inventors: Soeren H. Thomsen, Charles A. Sherwood, II, Casimir Karczewski
  • Patent number: 5596518
    Abstract: Stored in each of four coefficient memories are eight elements of each row of a matrix in 4 rows and 8 columns, which matrix consists of absolute values of elements of upper four rows out of an inverse discrete cosine matrix in 8 rows and 8 columns to be subjected to an 8-point IDCT processing. An input element y.sub.ij is supplied in parallel to four multipliers. Each of the four multipliers executes multiplication of an output of the corresponding coefficient memory out of the four coefficient memories, by the input element y.sub.ij. Eight accumulators are disposed for executing, in parallel, accumulation for obtaining eight inner products using results of the four multipliers while restoring signs of the coefficients of the orthogonal transform matrix. An 8-input selector is disposed for successively selecting results of the eight accumulators to supply an inner product w.sub.ij corresponding to the input element y.sub.ij.
    Type: Grant
    Filed: May 3, 1995
    Date of Patent: January 21, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaki Toyokura, Kiyoshi Okamoto, Yoshifumi Matsumoto
  • Patent number: 5596516
    Abstract: A code sequence generator having a register for holding n-bit code, and a calculation circuit for performing matrix calculation on the content of the register, and sequentially generating a code sequence by feeding back the calculation results to the register. The matrix which is set in the calculation circuit is changed by selectively reading a matrix from a memory circuit that stores precalculated matrices. This makes it possible to set a desired register state in a short time even if the desired code sequence is very long, and to generate any code sequences without changing the rate of a clock signal.
    Type: Grant
    Filed: April 25, 1995
    Date of Patent: January 21, 1997
    Assignee: NTT Mobile Communications Network Inc.
    Inventors: Akihiro Higashi, Koji Ohno, Narumi Umeda
  • Patent number: 5594672
    Abstract: A device that saves energy by turning on power to a peripheral device such as a printer only when a host computer sends data to its I/O port. When the peripheral device requires a warm-up period, the device will mediate the transition of the peripheral between a power-off state and a ready state by using a hold-off timer function.
    Type: Grant
    Filed: May 20, 1994
    Date of Patent: January 14, 1997
    Assignee: Micro Energetics Corporation
    Inventor: David S. Hicks
  • Patent number: 5594652
    Abstract: An object produces from a computer data base by representing the object in the data base as a solid voxels surrounded by support voxels within a volume. The data base representation of the object as the solid voxels is converted to a data base representation of the object as a shell of solid voxels surrounding filler support voxels, and the object from said converted data base representation is constructed in a layerwise fashion. A first material is dispensed in liquid form at selected locations of a target surface, and the selected locations correspond to the shell locations of a cross-section of an object. The first material solidifies after being dispensed; a second material is applied at locations of said target surface other than the shell locations at which the first material is dispensed, to form another target surface. The dispensing and applying is repeated to form an object comprising a shell of the first material surrounding said second material, and surrounded by the second material.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 14, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Steven M. Penn, David N. Jones, Michael E. Embree
  • Patent number: 5594743
    Abstract: A novel FIFO buffer system has an error detection and correction device for effectively detecting and correcting errors therein. The system comprises M number of data storage blocks arranged in parallel for temporarily storing N-bit input digital data and generating storage state signals including full flag and empty flag signals representative of the full and the empty states thereof; an error detector, responsive to the storage state signals, for generating full error signals and empty error signals representative of the errors present among the full flag signals and empty flag signals; and an error corrector, responsive to the full error and the empty error signals, for generating full error correction signals and empty error correction signals for correcting the erroneous storage state occurred in the corresponding data storage means thereto.
    Type: Grant
    Filed: November 9, 1994
    Date of Patent: January 14, 1997
    Assignee: Daewoo Electronics Co., Ltd.
    Inventor: Yong-Gyu Park
  • Patent number: 5594675
    Abstract: A digital FIR filter for producing an L phase interpolation of a input sample ##STR1## based on L filter banks and n tap coefficients P.sub.1 (i) in each 1.sup.th one of the filter banks is disclosed, where 1.ltoreq.1.ltoreq.L and where 0.ltoreq.i.ltoreq.(n-1). The digital filter includes a first circuit for producing, for each time t, bank filter terms of a merged bank filter having an output value which changes between a previous time t-1 and the time t. The produced bank filter terms include at least one combination of two cross-symmetric bank filter terms:for the in phase condition: ##STR2## and for the out of phase condition: the same as the in phase condition except that the parameter i in the product terms, ##STR3## are replaced by i-1, of the L filter banks on which the digital filter is based, where 1.ltoreq.k.ltoreq.L and for any non-negative integer w=0,1,2, . . . , t=w.multidot.L+k.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: January 14, 1997
    Assignee: Industrial Technology Research Institute
    Inventor: Yung-Chow Peng