Abstract: An N.sup.th order infinite impulse response digital filter for long-delay filtering of signals representing a digital input sequence. The N.sup.th order infinite impulse response digital filter is synthesized by cascading in series N first order infinite impulse response filter stages. A filter stage operable on a digital computer with floating point capability is provided and comprises a multiplier which multiplies an input signal with a weighting factor. A summing element provides an output for the filter stage by summing the weighted input signal with a weighted and delayed output signal. A filter operable on a digital computer with fixed point capability is provided and comprises a summing element which sums an input signal with the output of a first multiplier, and the delayed output of a mask element. The output of the summing element is coupled to the input of a second multiplier and to the input of the mask element.

Abstract: A process is disclosed for controlling a production machine, in particular an injection moulded machine that produces injection moulded plastic parts. During a learning cycle, rating fields that indicate the relationship between selected quality parameters of the products and selected setting parameters of the machine are determined and stored. To allow the machine to be controlled by entering the actual target values, i.e. the quality parameters of the products, the set values or set value ranges for at least two selected quality parameters are entered into a control device. The control device then determines at least one set of selected setting parameters on the basis of the stored rating fields, all predetermined quality parameters simultaneously corresponding to the predetermined set values or lying in the predetermine set value ranges.

Abstract: A moveable label printer-applicator/conveyor loader assembly for loading articles onto a conveyor comprises a frame mounted for movement along a conveyor path and a controller. The controller receives data from a host computer which specifies an article to be selected and actuates a drive motor to move the assembly to the selected bin location. The quantity of articles to be picked is displayed to an operator via a CRT display. Sensors detect the profile of articles loaded onto the conveyor and transmit this data to the controller. After the controller verifies that the correct article has been selected, a labeler prints and applies a label to each article.

Abstract: The present invention provides a signal loss recovery device (300; 400; 900) and method (500; 600; 1000; 1100; 1200) of digitally encoded bitstreams produced by predictive encoders, for realtime and/or interactive communications. The signal loss recovery device (300; 400; 900) of this invention recovers the lost or damaged information by requesting the transmitter for retransmitting the lost information. Compared to the previously known retransmission technique, the device in this invention does not introduce any extra buffer delay. The elimination of this buffer delay is realized by continuously processing the received data while waiting for the arrival of the retransmission. The information contained in the retransmitted data is reinserted into the error corrupted signal to restore the output signal to its original form without signal loss.

Abstract: An underflow/overflow detector includes first circuitry that decodes an exponent into an exponent shift value and compares the exponent shift value with a normalize shift value to determine whether an underflow or overflow error will occur. The underflow overflow detector further includes second circuitry that compares the exponent to a maximum and minimum exponent value to determine whether an underflow or overflow error will occur.

Abstract: A high speed digital polarity correlator includes a shift-one-bit circuit for receiving a first array, shifting the first array, and providing a one-bit shifted array, and a correlation circuit for delivering the correlation coefficient between a second and the one-bit shifted array. The correlation circuit includes an exclusive OR circuit receiving a data byte from each of the two arrays and delivering an XOR output containing a number of same states equal to the number of time the two arrays are in agreement. The conversion unit receives the XOR output and delivers a binary representation of a number of times the two arrays have been in agreement. An adder receives the number, adds the number to an existing sum of previous agreements between the two arrays and delivers an updated sum. A latch receives the updated sum, provides the updated sum as the existing sum to the adder, and, after all data bytes in the two arrays have been examined, delivers the correlation coefficient.

Abstract: A control system. An apparatus having a motor; a host processor for generating a message containing motor control information; a control board for receiving the message and for transmitting a command, corresponding to the message, to the motor; and a communications medium coupling the host processor and the control board. The communications medium supports a first communications path and a second communications path. The first communications path is for transmitting messages from the host processor to the control board. The second communications path is for transmitting messages from the control board to the host processor.

Abstract: A finite impulse response (FIR) filter is provided for shaping a one bit serial digital data pulse train in a digital data transmission system. The filter comprises (i) a delay element for sequentially receiving binary data bits in the data pulse train at fixed data cycle intervals and outputting simultaneously in parallel a plurality n of data bits representing a most recent history of the past n data bits received by the delay element during the past n data cycle intervals; (ii) a sampling element for sampling the data pulse train at a rate of m samples per bit, and (iii) a memory device having at least (n 30 m) address lines for providing at least 2.sup.(n+m) address locations. The n data bits and m samples provide an input to the address lines, the memory device in response providing a specific precomputed and stored output value for each possible combination of address line inputs.

Abstract: A method and means for detecting spectral null sequences of a spectrally-constrained code at the output of a noisy communications channel by tracking the spectral content of said sequences with a Viterbi detector using an N stage trellis and mapping each spectral null sequence to a unique path of acyclic successive states and edges through said trellis by selectively outsplitting counterpart states at preselected times modulo N in said trellis such that no pair of unique paths support the same spectral null sequence.

Abstract: A novel allocation method for generating a feasible production schedule. The method, in response to a specified requirement q, comprises the steps of determining what quantity (r) of a product can be produced with a specified quantity of supply components; allocating a required quantity of supply components for filling a thus defined partial order; and filling a remainder of the requirement (q-r) at some later time.

Abstract: An automatic library system for providing computer access to data carriers therein includes a store for the data carriers, and at least one read/write station for the data carriers having an in/out opening. An intermediate store is arranged adjacent the in/out opening for an intermediate storage of the data carders in at least one intermediate storage position. A controller is provided which is capable of initiating transportation of one of the data carders directly from said store to the in/out opening or from the store to the intermediate store. The controller is also capable of initiating transportation of one of the data carriers stored in the intermediate store to the in/out opening of the read/write station upon a request for the one of the data carders by the computer. In such a manner, operational delays for the automatic library system are significantly reduced.

Abstract: In a breakout prediction system for predicting breakout in a mold of a continuous casting machine, a prediction deciding section is connected to one of temperature sensors located on the mold and at least three temperature sensors which are adjacent to the one of the temperature sensors. In the prediction deciding section, at least three cross-correlators are connected to the one of the temperature sensors and the at least three temperature sensors and carry out a predetermined normalization operation to produce operation results. A temperature variation pattern detector is connected to the one of the temperature sensors to detect a temperature variation pattern. At least three peak detectors are connected to the at least three cross-correlators, respectively, to detect peak values of the operation results. At least three breakout detection networks are supplied with the peak values and the temperature variation pattern to carry out decision on breakout prediction.

Abstract: A notebook computer system with an easily separable trackball to give the system flexibility. The system makes use of a separable keyboard to achieve the goal of installing and separating the trackball. To this end the notebook computer comprises a keyboard that is able to be at least partially separated from the system, a socket for installation of the trackball module, with the trackball module being partially captured under the keyboard when installed in the socket. A notebook computer having a socket for accommodating a trackball may alternatively be provided with a plain plate, which allows the notebook computer to work normally without the trackball.

Abstract: A fixture process and method is provided for developing a complete set of all admissible fixture designs for a workpiece which prevents the workpiece from translating or rotating. The fixture processor generates the set of all admissible designs based on geometric access constraints and expected applied forces on the workpiece. For instance, the fixture processor may generate a set of admissible fixture designs for first, second and third locators placed in an array of holes on a fixture plate and a translating clamp attached to the fixture plate for contacting the workpiece. In another instance, a fixture vice is used in which first, second, third and fourth locators are used and first and second fixture jaws are tightened to secure the workpiece. The fixture process also ranks the set of admissible fixture designs according to a predetermined quality metric so that the optimal fixture design for the desired purpose may be identified from the set of all admissible fixture designs.

Abstract: A system for the manufacture of customized military uniform insignia badges begins with electronic entry of order data at the store locations. The order data is batched and electronically communicated to a remote manufacturing location where the order data, including custom text, is used to directly control the badge stamping machines.

Abstract: There is disclosed a control arrangement for plural consumer units allocated to groups for operation by means of operating elements connected with at least one group address control transmitter. The transmitter transmits group addresses to control receivers which are connected to customer units and in which group addresses are stored during a commissioning phase, whereby after such commissioning, consumer units are connected in groups with associated control receivers according to the operation of an operating element.

Abstract: A numerical control unit (NCU) uses character codes to communicate with an external input/output apparatus. Further, internal NCU data is stored in an array format corresponding to a display format. Further, while one set of data is being executed by the NCU, another set may be corrected by the user. Further, program data may be specified as variables rather than actual numerical values. Still further, memo data is provided to describe each piece of data. Finally, input program data is directly sent to a buffer where it is used to control a machining operation.

Abstract: A system for controlling a process system with a process system gain and dead time of which its transfer function includes a gain term element corresponding to the process system gain and a dead time term element corresponding to the dead time, subject to an external disturbance, by adjusting a control variable output by the process system to a target value according to a manipulated variable output by a controller performing at least proportional and integral control operations based on a deviation between the control variable and the target value.

Abstract: An energy management and home automation system includes one or more controllers in each facility being managed and one or more energy consuming devices attached to each controller. Each controller responds to digital paging signals from a central command center which establish a schedule of event effecting the operation of each device and the controller schedules each device to be operated pursuant to the programmed schedule. The user of the system, by appropriate communication with the command center, may cause a paging message to be provided at any time changing the pre-programmed schedule. The heating/cooling system is controlled by setpoint temperatures for each of a plurality of different modes of occupancy, whereby the most energy is consumed when the facility is occupied and lesser amounts of energy are consumed when the facility is empty. Intermediate amounts of energy are consumed when the facility is not fully operational because people are asleep or maintenance or cleaning is being done.

Abstract: A SIMM is provided which adds ECC onto a computer system, which system does not have ECC capabilities. The SIMM has ECC on board. The SIMM also has logic to sense whether the system is an "even" parity or "odd" parity system. Parity of the written data bytes is checked, and check bits used for the ECC are manipulated to check parity on the read cycle responsive to the sensed parity of the system. During the read cycle, parity is generated by the logic corresponding to the sensed system parity, and ECC is performed.