Patents Examined by Roy N. Envall, Jr.
  • Patent number: 5576965
    Abstract: In a design aiding method, a design aiding apparatus having the method, or a design aiding system possessing a plurality of such design aiding apparatuses for use in a field of computer software to facilitate a design process, there is determined, for a product having many variations of attributes and values thereof, an appropriate design procedure according to a state of design in a process of determining the attribute values of the product satisfying a request of a client. At occurrence of, for example, conflict during the design, the design procedure is guided for the user to obtain a design plan conforming to the request.
    Type: Grant
    Filed: April 12, 1993
    Date of Patent: November 19, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Shingo Akasaka, Yoshinao Arai, Atsuhiro Ishida, Noriyuki Haga, Katsuyoshi Katsuta, Shoji Arino, Yoko Tonosaki, Tomoko Ogawa
  • Patent number: 5576945
    Abstract: A multiple processor system includes at least one process pair each including a plurality of modules. The modules perform functions related to multiple independent threads, and are arranged in a predetermined order such that higher modules are dependent upon lower modules, and lower modules are independent from higher modules. Each process pair is initially unaware of the number and order of the modules. The order of the modules is related to dependency and interdependency between the modules so that there is a portion of higher modules and a portion of lower modules. Multiple independent threads process the modules to cause activities in the portions of higher modules to take place before activities in the portions of lower modules.
    Type: Grant
    Filed: January 23, 1995
    Date of Patent: November 19, 1996
    Assignee: Tandem Computers Incorporated
    Inventors: Matthew C. McCline, James M. Lyon
  • Patent number: 5574735
    Abstract: In an error correction circuit, when a data loss is detected, substitute data comprising all bits of "1" or "0" are generated during a data loss period and substituted for the lost data for the data loss period. Thereafter, the whole data containing the substitute data are decoded in a predetermined error correction system to generate corrected data.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: November 12, 1996
    Assignees: Nippon Hoso Kyokai, Nippon Conlux Co., Ltd.
    Inventors: Masayuki Takada, Osamu Yamada, Toru Kuroda, Koichi Yamazaki
  • Patent number: 5574670
    Abstract: When a data input signal having R plus X groups of M digits is received, the digits are segmented such that X different first counter-detectors receive M digits and a second counter-detector receives the R digits. The counter-detectors determine a number of most significant count digits leading a most significant non-count digit and detect the presence of a non-count digit. A decoder receives the outputs of the first counter-detectors and, responsive to a non-count digit detection in a most significant group of M digits having a non-count digit, communicates the corresponding count number to a concatenator. A third counter-detector determines and communicates a number of most significant groups of M digits having no non-count digits. An output of the third counter detector is concatenated with an output of the decoder where the decoder output is represented by Z digits where M=N.sup.Z (X, M, R, N, and Z are non-negative integers). The concatenation represents the number of leading count digits.
    Type: Grant
    Filed: August 24, 1994
    Date of Patent: November 12, 1996
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Leonel Lozano
  • Patent number: 5574736
    Abstract: An improved storage device, such as a disk drive, for use in an array of drives. Each drive has logic and Exclusive Or calculation means. Data to be written is sent to the target disk drive from the host computer under a new command that instructs the target drive to generate part of the new parity, and may also identify the parity drive. The target device reads the old data from it's media, generates a parity syndrome, stores the new data and then initiates communication with the identified parity drive, instructing the parity drive to read the old parity and generate the new parity information from the parity syndrome and the old parity. The parity drive, after generating the new parity, writes the new parity onto it's media, all without further host or host I/O action.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: November 12, 1996
    Assignee: International Business Machines Corporation
    Inventor: Peter B. Bandy
  • Patent number: 5574673
    Abstract: A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of the logic circuitry are switched among the cells. The architecture disclosed and claimed herein generates an identical sequence while consuming substantially less power than a linear feedback shift register implementation. The parallel architecture may also be used to implement a parallel shift register in other applications.
    Type: Grant
    Filed: November 29, 1994
    Date of Patent: November 12, 1996
    Assignee: Board Of Regents, The University Of Texas System
    Inventor: Menahem Lowy
  • Patent number: 5574638
    Abstract: A process control system which includes at least one manipulated variable and at least one controlled variable, provides a method for robust control of a process. Predetermined constraints of the manipulated variables and the controlled variables, and the present values of the manipulated variables are obtained. A set of scale factors for the manipulated variables and the process variables are calculated. The controller is initialized with the set of scale factors, the scale factors determining the relative importance of the manipulated variables and the process variables to the process. New values are calculated for the controlled variables for a predetermined number of points in the future, such that the values of the controlled variables are within the predetermined range thereby obtaining an optimal robustness of the resultant controller.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: November 12, 1996
    Inventor: Zhuxin J. Lu
  • Patent number: 5574674
    Abstract: A process for suppressing the Gibbs phenomenon in a train of digital signals when such signals are undergoing a discrete Fourier transform or a fast Fourier transform without using the conventional windowing techniques wherein the original function defined by the initial set of digital signals is changed into a new function so that the first and last data points thereof are made equal to make the waveform of the new function each a complete cycle within its DFT period while the interrelationship of the remaining data points remain as in the original function, so that no spurious frequency components are introduced in the digital signal output. The process is shown as used in an all-purpose digital filter.
    Type: Grant
    Filed: March 14, 1994
    Date of Patent: November 12, 1996
    Inventor: Cheh Pan
  • Patent number: 5574677
    Abstract: The number of steps to perform integer division is reduced by combining detection of a remainder overflow with the final remainder restore step. When the sign bit of the partial remainder flips during the restore step, then there is no remainder overflow. However, when the sign bit does not change, then a remainder overflow is signaled. For signed division, the final quotient before a final complementation is also examined. This quotient should be a positive number since the dividend is initialized to a positive number, and the divisor is added or subtracted at each iteration assuming that it was a positive number. If the final quotient is negative, then an overflow is signaled except in a special case. If the quotient is the minimum integer, MININT, the most-negative number representable, and the expected sign is negative, then an overflow has not occurred. MININT is detected by ORing together the low bits in the quotient.
    Type: Grant
    Filed: November 23, 1994
    Date of Patent: November 12, 1996
    Assignee: Exponential Technology, Inc.
    Inventor: Earl T. Cohen
  • Patent number: 5574652
    Abstract: A control system for controlling multiple operations of a machine tool includes an electronic controller. The controller is programmed to execute sequences of command instructions, each sequence representing a group of command instructions which defines a single operation or unit of work for the machine tool. A plurality of sequences are grouped together to define a machine cycle for the machine tool. An input mechanism is provided for permitting an operator of the machine tool to generate control signals to the controller to control the operation thereof. A video display is also provided for permitting an operator of the machine tool to monitor the operation thereof. The video display shows a plurality of the sequences in the machine cycle for performing certain functions when operated in the forward mode, as well as the corresponding sequences in the machine cycle for performing the opposite functions when operated in the reverse mode.
    Type: Grant
    Filed: February 17, 1993
    Date of Patent: November 12, 1996
    Assignee: Dana Corporation
    Inventor: Michael A. Murphy
  • Patent number: 5572433
    Abstract: A system is disclosed for detecting watermarks or other marks made along a web of paper at regular intervals. The watermarks are detected by a video camera activated by a frame grabbing pulse in a control loop. The video for each frame grab pulse signal is digitized and processed to detect the watermark and to measure its position within the frame. The error between the measured position and a frame reference is used to adjust the value of a parameter (NEWCOUNT) representing the distance or pitch between successive watermarks. This value is in turn used to determine the moment of the next or a succeeding frame grab pulse. All timing is done in terms of measured length of web run by measuring pulses from an encoder. The control loop acts to track variations in the watermark pitch.
    Type: Grant
    Filed: July 8, 1993
    Date of Patent: November 5, 1996
    Assignee: The Wiggins Teape Group Limited
    Inventors: Andrew P. Falconer, Peter T. Herdman
  • Patent number: 5572434
    Abstract: An efficient numerical procedure for the simulation of Newtonian fluids with non-negligible inertial effect which satisfies the Navier-Stokes equations and the energy equation. The method simulates the molding-filling process of incompressible viscous liquid, e.g. semi-solid metal, in a thin and irregular cavity. The moving free surfaces in an irregular domain is tracked using a fixed-mesh method. The material discontinuities across the interface between air and the liquid are removed by replacing the air with a pseudo-gas which has small density and dynamic viscosity but its kinematic viscosity is the same as that of the liquid. During the filling process, the (semi-solid) liquid may solidify on the mold surface. As a result, the effective cavity thickness reduces non-uniformly according to the result thermal analysis. The Navier-Stokes equations are integrated across the remaining gap by assuming that the velocity profile (not magnitude) is similar to that in a fully-developed flow.
    Type: Grant
    Filed: June 14, 1994
    Date of Patent: November 5, 1996
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Kuo K. Wang, Shau-Poh Wang
  • Patent number: 5572430
    Abstract: In order to derive optimum design specifications based on total evaluation performed on a product as a whole instead of individual design items during a process of determining design specifications involving a plurality of design items, candidates for the product specifications are selected by controlling design parameters for each of the design items in an integrated manner, computing values of a plurality of evaluation items evaluating candidates for the design specifications and performing total evaluation on all the evaluation items based on their computed values through collaboration among a plurality of design sections altogether auto-correcting all relevant design parameters quickly and relaxing as well as reassessing design constraints for a design parameter.
    Type: Grant
    Filed: June 29, 1992
    Date of Patent: November 5, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Shingo Akasaka, Sugino Kazuhiro, Hiroko Imanishi, Junichi Saeki, Kunihiko Nishi
  • Patent number: 5572431
    Abstract: A method and apparatus for forming a three-dimensional article includes dispensing build material and thermally normalizing predetermined portions thereof at predetermined intervals during construction of the article. The thermal energy may be provided by a heated body advanced adjacent to or in contact with the surface portions. Thermal energy may also be supplied by a radiation source. The thermal normalization may be performed after a predetermined number of successive layers are dispensed. Related methods are also disclosed.
    Type: Grant
    Filed: October 19, 1994
    Date of Patent: November 5, 1996
    Assignee: BPM Technology, Inc.
    Inventors: Robert B. Brown, Charles F. Kirschman, Herbert E. Menhennett
  • Patent number: 5570292
    Abstract: An integrated system for selecting, ordering and manufacturing art glass panels is provided. An artistic art glass design is combined with a set of design rules specifically applicable to such art glass design to produce a digitized data file uniquely identifying the art glass design. The digitized data file information is used to reconfigure the initial art glass design, according to the entered set of design rules, to conform the art glass design to the unique panel size and shape requirements of a customer. A data file of the reconfigured art glass panel information is forwarded to the manufacturer. The digitized reconfigured file data includes all of the information regarding component sizes, shapes and cutting and assembly instructions required to enable automated assembly and costing for the art glass panel fabrication.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: October 29, 1996
    Assignee: Andersen Corporation
    Inventors: Loren Abraham, Michael F. Pilla, Jason Bright
  • Patent number: 5570305
    Abstract: A signal that may be represented by a band limited periodic function m(t) is transformed into its z-domain zeros using characteristics of the signal in the neighbourhood of fades of the signal, namely a bounds of the fades and the depths of the fades. The z-domain zeros are the zeros of the function in the complex plane, and represent local minimums of the function. The z-domain zeros are used to estimate the discrete spectrum of m(t), and the differential phase of m(t) is derived from the envelope of m(t) using the concept of the z-domain zeros. Also, speech is compressed based on the z-domain zeros of a signal m(t) that represents a speech signal, and knowledge of the location of fades is used in interference reduction at single moving antennas by applying a spectral resolution technique during a fade and applying notch filters to the signal to resolve the signal components.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: October 29, 1996
    Inventors: Michel Fattouche, Hatim Zaghloul
  • Patent number: 5570306
    Abstract: A method and apparatus for recognizing a search pattern in an input string of bits is provided. According to one aspect of the invention, a portion of the string of bits is selected as a currently selected portion. Based upon the search pattern and the bits of the string of bits immediately preceding the currently selected portion, a first set of occurrence patterns is determined. The first set of occurrence patterns is determined such that if any of the occurrence patterns in the first set of occurrence patterns are contained in the currently selected portion of the string of bits, the string of bits contains the search pattern. A determination is then made whether the currently selected portion contains any of the occurrence patterns in the first set of occurrence patterns. Thus, based on whether the currently selected portion contains any of the occurrence patterns in the first set of occurrence patterns, it is determined whether the string of bits contains the search pattern.
    Type: Grant
    Filed: November 1, 1994
    Date of Patent: October 29, 1996
    Assignee: Intel Corporation
    Inventor: Paul J. Soo
  • Patent number: 5570377
    Abstract: A method and device for detection and correction of errors in ATM cell headers, wherein it series to parallel converts (2) the serial data stream (1), thereby obtaining a parallel data format of n bits, the clock rate of which is n times lower than the original. From the parallel input data of the ATM header, a syndrome word (3) is generated according to a determined function that indicates that no error has been detected, that more than one error has been detected, or which bit has to be corrected when only one error has been detected. The ATM cell headers are delayed (4) until the syndrome word has been completed, the error correction process (5) then being carried out, when required, in accordance with the syndrome word generated. In addition, an individual indication (7) for external use is generated of the result of the detection and possible correction process made. The device implements the method described.
    Type: Grant
    Filed: November 29, 1993
    Date of Patent: October 29, 1996
    Assignee: Alcatel N.V.
    Inventors: Jose L. Merino Gonzalez, Carmen maria L. Cabello, deceased
  • Patent number: 5570293
    Abstract: Semiconductor chip manufacturing methods and devices are disclosed which store dicing data corresponding to the kinds of wafers, when data indicating the wafer kinds are input, read out the dicing data corresponding to the data input, and cut a wafer set at a given position to a desired shape in accordance with the dicing data to thereby manufacture a semiconductor chip. The manufacturing methods and devices include read means for inputting the data indicating the wafer kinds. According to the manufacturing method and device, a symbol indicating the kind of the wafer is recorded as an identification symbol readable by the read means and on a member moving together with the wafer in a chip manufacturing process that is not part of the product being manufactured, and preferably, is also not part of a recyclable carrier for the wafer to be diced. When the data indicating the kind of the wafer is input, the identification symbol recorded in the above-mentioned member is read out by the read means.
    Type: Grant
    Filed: June 29, 1994
    Date of Patent: October 29, 1996
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventors: Toshiyuki Tanaka, Masaharu Nakamura
  • Patent number: 5570378
    Abstract: In an error-correcting apparatus for correcting errors included in reproduced data which are stored in a RAM, a syndrome generation circuit, a polynomial calculation circuit for calculating an error position polynomial and an error value polynomial, and a position calculation circuit for calculating an error position are operated in parallel. A divider section of the error-correcting apparatus has a divider for performing the division of highest-degree coefficients of two polynomials, a multiplier for multiplying the coefficient of the polynomial set in the divisor side of the divider by the output of the divider, and an adder for adding the output of the multiplier and the coefficient of the polynomial set in the dividend side of the divider. The divider section executes the division over a Galois field while sequentially shifting the contents of registers which store the coefficient data of the dividend polynomial.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: October 29, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Sadayuki Inoue, Junko Ishimoto, Takahiko Nakamura, Makoto Kumano