Patents Examined by Roy Potter
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Patent number: 9613894Abstract: An electronic package is provided. The electronic package includes an insulator having a recessed portion formed therein; an electronic element embedded in the recessed portion and having a sensing region exposed from the insulator; and a conductive structure disposed on the insulator and electrically connected with the electronic element. The overall thickness of the electronic package is reduced by embedding the electronic element which is embedded in the recessed portion.Type: GrantFiled: January 8, 2016Date of Patent: April 4, 2017Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Chu-Chin Hu, Shih-Ping Hsu
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Patent number: 9613865Abstract: The present disclosure provides die cutting methods and semiconductor dies. A semiconductor substrate has a test region, isolation regions, and core regions. A device layer, an interconnection layer, and a soldering pad layer are formed on the semiconductor substrate. The soldering layer includes a plurality of soldering pads. A passivation layer covers the soldering pads and the interconnect layer, and is etched to form trenches on the soldering pads above the core regions and the test region. The passivation layer, the interconnect layer, and the device layer are etched to form isolation trenches at junctions of the isolation region and the test region, disconnecting the passivation layer, the interconnect layer and the device layer. A cutting process is performed along the test region, each of the semiconductor substrate, the device layer, the interconnect layer and the soldering pad layer is cut in two.Type: GrantFiled: January 8, 2016Date of Patent: April 4, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Jyishyang Liu, Xuanjie Liu, Xiaojun Chen, Lushan Jiang
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Patent number: 9608058Abstract: A semiconductor device includes a SiC layer that has a first surface and a second surface, a first electrode in contact with the first surface, a first SiC region of a first conductivity type in the SiC layer, a second SiC region of a second conductivity type in the SiC layer and surrounding a portion of the first SiC region, a third SiC region of the second conductivity type in the SiC layer and surrounding the second SiC region, the third SiC region having an impurity concentration of the second conductivity type lower than that of the second SiC region, and a fourth SiC region of the second conductivity type in the SiC layer between the second SiC region and the third Sic region, the fourth SiC region having an impurity concentration of the second conductivity type higher than that of the second SiC region.Type: GrantFiled: March 7, 2016Date of Patent: March 28, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Ryoichi Ohara, Takao Noda, Yoichi Hori
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Patent number: 9608097Abstract: The present invention provides a lateral IGBT transistor comprising a bipolar transistor and an IGFET. The lateral IGBT comprises a low resistive connection between the drain of the IGFET and the base of the bipolar transistor, and an isolating layer arranged between the IGFET and the bipolar transistor. The novel structure provides a device which is immune to latch and gives high gain and reliability. The structure can be realized with standard CMOS technology available at foundries.Type: GrantFiled: May 12, 2014Date of Patent: March 28, 2017Assignee: K.EKLUND INNOVATIONInventor: Klas-Hakan Eklund
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Patent number: 9607920Abstract: Methods for depositing silicon on a semiconductor or metallic surface include cycling dosing of silane and chlorosilane precursors at a temperature between 50° C. and 300° C., and continuing cycling between three and twenty three cycles until the deposition self-limits via termination of surface sites with Si—H groups. Methods of layer formation include depositing a chlorosilane onto a substrate to form a first layer, wherein the substrate is selected from the group consisting of InxGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99. The methods may include pulsing a silane to form a silicon monolayer and cycling dosing of the chlorosilane and the silane. Layered compositions include a first layer selected from the group consisting of InxGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99, and a second layer, wherein the second layer comprises Si—H and Si—OH.Type: GrantFiled: March 4, 2016Date of Patent: March 28, 2017Assignees: APPLIED MATERIALS, INC., The Regents of the University of CaliforniaInventors: Mary Edmonds, Andrew C. Kummel, Atif M. Noori
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Patent number: 9607997Abstract: A wide trench having a width W1 and narrow trenches having a width W2 that is less than W1 are formed in a dielectric layer, the wide trench extending deeper in outer regions than in a central region. A trench modification step changes the width of the wide trench and reduces a depth difference between the outer regions and the central region of the wide trench.Type: GrantFiled: September 8, 2015Date of Patent: March 28, 2017Assignee: SANDISK TECHNOLOGIES INC.Inventors: Katsuo Yamada, Yuji Takahashi, Noritaka Fukuo, Masami Uozaki, Kiyokazu Shishido, Takuya Futase, Shunsuke Watanabe
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Patent number: 9597752Abstract: A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.Type: GrantFiled: October 21, 2015Date of Patent: March 21, 2017Assignee: MEDIATEK INC.Inventors: Tao Cheng, Wen-Sung Hsu, Shih-Chin Lin
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Patent number: 9601720Abstract: An organic light emitting diode display includes a plurality of switches, a plurality of organic light emitting diodes respectively connected to the switches, and a polarization layer on the organic light emitting diodes. The polarization layer includes a light blocking area and a plurality of color filters. The light blocking area has a plurality of openings respectively exposing the organic light emitting diodes. The color filters respectively fill the openings. A first dot opening includes a first red opening, a first green opening, and a first blue opening elongated in a first direction. A second dot opening includes a second red opening, a second green opening, and a second blue opening elongated in a second direction crossing the first direction.Type: GrantFiled: October 26, 2015Date of Patent: March 21, 2017Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Jin Woo Choi, Jae Ik Lim, Hae Yun Choi
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Patent number: 9601163Abstract: A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal.Type: GrantFiled: May 31, 2016Date of Patent: March 21, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Hyung Song, Kyoungsun Kim, Yong-Jin Kim, Jaejun Lee, Sangseok Kang, Jungjoon Lee
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Patent number: 9601402Abstract: A package apparatus comprises a first wiring layer, a metal layer, a conductive pillar layer, a passive component, a first molding compound layer, a second wiring layer, and a protection layer. The first wiring layer has a first surface and a second surface opposite to each other. The metal layer is disposed on the first surface of the first wiring layer. The conductive pillar layer is disposed on the second surface of the first wiring layer. The passive component is disposed on the second surface of the first wiring layer. The first molding compound layer is disposed within a part of the zone of the first wiring layer and the conductive pillar layer. The second wiring layer is disposed on the first molding compound layer and one end of the conductive pillar layer. The protection layer is disposed on the first molding compound layer and the second wiring layer.Type: GrantFiled: October 3, 2014Date of Patent: March 21, 2017Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: E-Tung Chou, Chu-Chin Hu, Shih-Ping Hsu
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Patent number: 9595694Abstract: A thin film transistor (TFT) substrate which may facilitate subsequent TFT processing by reducing an elevation difference on the top surface of the substrate is disclosed. Aspects include an organic light-emitting apparatus including the TFT substrate, a method of manufacturing the TFT substrate, and a method of manufacturing the organic light-emitting apparatus. In one aspect the TFT substrate includes: a substrate; a height adjusting layer that is disposed on the substrate and has a thickness in a first region greater than a thickness in a second region; and a TFT that is formed on the height adjusting layer to correspond to the second region of the height adjusting layer.Type: GrantFiled: August 29, 2013Date of Patent: March 14, 2017Assignee: Samsung Display Co., Ltd.Inventor: Dong-Won Lee
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Patent number: 9595530Abstract: A method is provided that includes forming a first vertical bit line disposed in a first direction above a substrate, forming a first word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, forming a first memory cell comprising a nonvolatile memory material at an intersection of the first vertical bit line and the first word line, forming a transistor above the substrate, and forming a first bit line select device coupled between the first vertical bit line and the transistor.Type: GrantFiled: July 7, 2016Date of Patent: March 14, 2017Assignee: SanDisk Technologies LLCInventor: Guangle Zhou
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Patent number: 9590103Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.Type: GrantFiled: January 8, 2016Date of Patent: March 7, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Yoon Hae Kim, Jin Wook Lee, Jong Ki Jung, Myung II Kang, Kwang Yong Yang, Kwan Heum Lee, Byeong Chan Lee
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Patent number: 9589908Abstract: A method and apparatus are provided for manufacturing a packaged electronic device (200) which includes a carrier substrate (120) in which conductive interconnect paths (122) extend between first and second opposed surfaces, an integrated circuit die (125) affixed to the first surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, and an array of conductors (110), such as BGA, LGA, PGA, C4 bump or flip chip conductors, affixed to the second surface of the carrier substrate for electrical connection to the plurality of conductive interconnect paths, where the array comprising a signal feed ball (112) and an array of shielding ground balls (111) surrounding the signal feed ball.Type: GrantFiled: September 29, 2015Date of Patent: March 7, 2017Assignee: NXP USA, INC.Inventor: Walter Parmon
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Patent number: 9583489Abstract: A method of forming a semiconductor device comprises forming a first fin on a substrate, depositing an insulator layer on the substrate adjacent to the first fin, removing a first portion of the insulator layer to expose a first portion of a sidewall of the first fin, depositing a layer of spacer material over the first portion of the sidewall of the first fin, removing a second portion of the insulator layer to expose a second portion of the sidewall of the first fin, depositing a first glass layer including a first doping agent over the exposed second portion of the sidewall of the first fin, and performing a first annealing process to drive the first doping agent into the first fin.Type: GrantFiled: January 8, 2016Date of Patent: February 28, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent A. Anderson, Hemanth Jagannathan, Sanjay C. Mehta, Balasubramanian Pranatharthiharan
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Patent number: 9577046Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface, a first electrode on the first surface, a second electrode on the second surface, a first semiconductor region of a first conductivity type in the semiconductor layer, a second semiconductor region of a second conductivity type in an element region of the semiconductor layer between the first semiconductor region and the first electrode, a third semiconductor region of the second conductivity type between the second semiconductor region and the first electrode, and a fourth semiconductor region of the second conductivity type in a termination region of the semiconductor layer inwardly of the first surface. A distance between the fourth semiconductor region and the second surface is greater than a distance between the second semiconductor region and the second surface.Type: GrantFiled: March 7, 2016Date of Patent: February 21, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Yoichi Hori, Tsuyoshi Oota, Hiroshi Kono, Atsuko Yamashita
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Patent number: 9576901Abstract: A method for manufacturing a semiconductor device includes forming a contact area opening in a dielectric structure, depositing a contact area metal in the contact area opening, forming a metal cap layer on the contact area metal, forming one or more dielectric layers on the metal cap layer, forming one or more hard mask layers on the one or more dielectric layers, forming a metallization opening through the one or more dielectric and hard mask layers, wherein the metallization opening exposes the metal cap layer, removing the one or more hard mask layers, and forming a metallization layer in the metallization opening on the metal cap layer.Type: GrantFiled: February 25, 2016Date of Patent: February 21, 2017Assignee: International Business Machines CorporationInventors: Hsueh-Chung Chen, Su Chen Fan, Chih-Chao Yang
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Patent number: 9576905Abstract: A semiconductor device includes a first wiring comprising a first conductive material on a semiconductor layer, a second wiring comprising the first conductive material on the semiconductor layer, a third wiring comprising a second conductive material different from the first conductive material, and an insulation film on the semiconductor layer between the first wiring and the second wiring and between the second wiring and the third wiring. The second wiring is provided on at least two sides of the third wiring, and a mean free path of free electrons in the first conductive material is shorter than a mean free path of free electrons in the second conductive material, or the first conductive material shows quantized conduction and the second conductive material does not show quantized conduction. The first wiring, the second wiring, the third wiring, and the insulation film are in one wiring layer provided on the semiconductor layer.Type: GrantFiled: February 24, 2016Date of Patent: February 21, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Taishi Ishikura, Atsunobu Isobayashi, Akihiro Kajita
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Patent number: 9567208Abstract: A semiconductor structure includes a first device, a second device, a first hole, a second hole, and a sealing object. The second device is contacted to the first device, wherein a chamber is formed between the first device and the second device. The first hole is disposed in the second device and defined between a first end with a first circumference and a second end with a second circumference. The second hole is disposed in the second device and aligned to the first hole. The sealing object seals the second hole. The first end links with the chamber, and the first circumference is different from the second circumference.Type: GrantFiled: November 6, 2015Date of Patent: February 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Wen Cheng, Yi-Chuan Teng, Cheng-Yu Hsieh, Lee-Chuan Tseng, Shih-Wei Lin
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Patent number: 9570321Abstract: A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a surface defined by a wafer level package (WLP) region and an external region, and a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer.Type: GrantFiled: October 20, 2015Date of Patent: February 14, 2017Assignee: RAYTHEON COMPANYInventors: Stephen H. Black, Adam M. Kennedy