Abstract: By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode.

Abstract: Packages and 3D die stacking processes are described. In an embodiment, a package includes a second level die hybrid bonded to a first package level including a first level die encapsulated in an oxide layer, and a plurality of through oxide vias (TOVs) extending through the oxide layer. In an embodiment, the TOVs and the first level die have a height of about 20 microns or less.

Abstract: A light emitting device may include a substrate, a light emitting structure disposed under the substrate, the light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, a first electrode configured to penetrate the second conductive semiconductor layer and the active layer, so as to come into contact with the first conductive semiconductor layer, a contact layer configured to come into contact with the second conductive semiconductor layer, a first insulation layer disposed between the second conductive semiconductor layer and the first electrode and between the active layer and the first electrode, the first insulation layer being provided for capping of a side portion and an upper portion of the contact layer, and a second electrode configured to penetrate the first insulation layer, so as to come into contact with the contact layer.

Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

Abstract: An integrated capacitor can be fabricated with both electrodes formed by trenches for low resistance. According to one embodiment, the capacitor can comprise a first trench electrode, one or more dielectric layers, and a second trench electrode. The first trench electrode and the second trench electrode can be fabricated in different trenches to improve capacitance density and resistance of the integrated capacitor.

Abstract: An electronic device includes a drive substrate (a pressure chamber substrate and a vibration plate) including a piezoelectric element and electrode wirings related to driving of the piezoelectric element formed thereon, and a sealing plate bonded thereto, the electrode wirings are made of wiring metal containing gold (Au) on the drive substrate through an adhesion layer which is a base layer, and has a removed portion in which a portion of the wiring metal in a region containing a part bonded to a bonding resin is removed and the adhesion layer is exposed.

Abstract: A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metalization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 ?m larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.

Abstract: A semiconductor device includes: a buffer layer formed over a substrate; a first semiconductor layer formed over the buffer layer by using a compound semiconductor; a second semiconductor layer formed over the first semiconductor layer by using a compound semiconductor; and a gate electrode, a source electrode, and a drain electrode formed over the second semiconductor layer, wherein the first semiconductor layer contains an impurity element serving as an acceptor and an impurity element serving as a donor; and in the first semiconductor layer, an acceptor concentration of the impurity element serving as the acceptor is greater than a donor concentration of the impurity element serving as the donor; and the donor concentration is greater-than over equal to 5×1016 cm?3.

Abstract: A semiconductor memory device according to an embodiment comprises a stacked body, a semiconductor layer, a charge accumulation layer, and a slit portion. The stacked body includes a plurality of control gate electrodes stacked above a substrate. The semiconductor layer has one end thereof connected to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. The slit portion extends in a direction of the substrate from a surface of the stacked body, wherein the slit portion has its longitudinal direction in a direction intersecting the first direction.

Abstract: Disclosed is a light emitting device. The light emitting device includes a body, first and second metal layers on a top surface of the body, a heat radiation plate disposed between the first and second metal layers and having a circular outline, a plurality of light emitting parts on the heat radiation plate, first and second bonding regions disposed on the first and second metal layers and electrically connected with the light emitting parts, and a molding member disposed on the heat radiation plate to cover the light emitting parts. Each of the light emitting parts includes a plurality of light emitting chips connected with each other, and a plurality of wires to electrically connect the light emitting chips with the first and second bonding regions, and the wires of each light emitting part are arranged a radial direction about a central of the heat radiation plate.

Abstract: One semiconductor device includes one parallel transistor for connecting in parallel multiple vertical transistors disposed in an active region on a semiconductor substrate. The parallel transistor includes semiconductor pillars that project out in a direction perpendicular to a main surface of the semiconductor substrate; a lower diffusion layer that is disposed below the semiconductor pillars; upper diffusion layers that are each disposed on an upper section of the semiconductor pillars; and gate electrodes disposed, with a gate insulator film therebetween, on the entire side surfaces of the semiconductor pillars. The upper diffusion layers are connected to one upper contact plug that is disposed over the upper diffusion layers.

Abstract: In one embodiment, an electronic package structure includes a lead having a first width. An electronic chip having a conductive bump on a major surface, the conductive bump has a second width greater than the first width. The conductive bump is attached to the lead such that a portion of the conductive bump extends to at least partially surround a side surface of the lead. A molding compound resin encapsulates the electronic chip, the conductive bump, and at least a portion of the lead. The lead is configured so strengthen the joining force between the lead and conductive bump.

Abstract: A semiconductor chip includes a semiconductor substrate having a front surface, a circuit unit formed within the semiconductor substrate and extending from the front surface into the semiconductor substrate, and a rear surface opposite the front surface, and a girder beam disposed outside of the circuit unit and within the semiconductor substrate.

Abstract: FinFET transistor comprising at least: one fin that forms a channel, a source and a drain, comprising an alternating stack of first portions of silicon-rich SiGe and of second portions of a dielectric or semiconductor material, and third portions of germanium-rich SiGe arranged at least against lateral faces of the first portions, one gate that covers the channel, and wherein each one of the third portions comprises faces with a crystal orientation [111] covered by the gate.

Abstract: A semiconductor device includes: a semiconductor chip, and a lead frame. The semiconductor chip is mounted over a die pad. Four suspension leads are connected with the die pad and at least one of them is provided between first and second lead groups and is deformed to protrude toward the first lead group. At least one of the leads of the second lead group which is nearer to the deformed suspension lead is deformed to be apart from remaining leads of the second lead group.

Abstract: RF transmission device including at least: a substrate comprising first and second faces opposite to each other; a first RF transmission electronic circuit arranged on and/or in the substrate; a first antenna arranged on the side of the first face of the substrate, spaced apart from the first face of the substrate and electrically connected to the first RF transmission electronic circuit; a first electromagnetic wave reflector coupled to the first antenna and including: a first high impedance surface comprising at least several first electrically conducting elements forming a first periodic structure and arranged on the first face of the substrate opposite the first antenna; a first electrically conducting ground plane arranged at least partially opposite the first antenna.

Abstract: To provide is a p-type oxide, including an oxide, wherein the oxide includes: Cu; and an element M, which is selected from p-block elements, and which can be in an equilibrium state, as being present as an ion, wherein the equilibrium state is a state in which there are both a state where all of electrons of p-orbital of an outermost shell are lost, and a state where all of electrons of an outermost shell are lost, and wherein the p-type oxide is amorphous.

Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.