Abstract: A hollow frame is configured to surround the periphery of a substantially self-supporting flip-chip light emitting device. The frame may be shaped to also contain a wavelength conversion element above the light emitting surface of the light emitting device. The lower surface of the light emitting device, which is exposed through the hollow frame, includes contact pads coupled to the light emitting element for surface mounting the light emitting module on a printed circuit board or other fixture. The flip-chip light emitting device may include a patterned sapphire substrate (PSS) upon which the light emitting element is grown, the patterned surface providing enhanced light extraction from the light emitting element, through the patterned sapphire substrate.

Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.

Abstract: 3D Stacked memory devices with copper pillars electrically connecting the package units are disclosed. A stacked package-on-package memory device includes a base chip package unit having a logic processing chip disposed on a base substrate; and a memory chip stack overlying the base chip unit. The memory chip stack includes a stack of packaged memory units. Each packaged memory unit including a memory chip on an IC substrate. Copper pillars are disposed on the back side of the IC substrate and electrically connected to the base substrate.

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate and a first die coupled to a top surface of the substrate. A second die is coupled to a bottom surface of the substrate. A thermal contact pad couples the second die to the bottom surface of the substrate. The thermal contact pad electrically isolates the first die from the second die. A molding compound resides over the substrate and surrounds the first and second dies and the thermal contact pad.

Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first ridge portion embedded in the first concave and the drain includes a second ridge portion embedded in the second concave, wherein the first and second ridge portions extend along a height direction of the semiconductor fin.

Abstract: An organic EL device includes a substrate and a plurality of organic EL elements disposed on the substrate. Each of the plurality of organic EL elements includes a light-emitting layer containing a light-emitting material. One of the plurality of organic EL elements includes a first film containing the same light-emitting material as the light-emitting layer of another one of the plurality of organic EL elements, the first film being in contact with an upper surface of the light-emitting layer of the one of the plurality of organic EL elements. The one of the plurality of organic EL elements does not include a second film containing the same light-emitting material as the light-emitting layer of another one of the plurality of organic EL elements, the second film being in contact with a lower surface of the light-emitting layer of the one of the plurality of organic EL elements.

Abstract: A semiconductor variable resistance device includes: a substrate; a gate formed on the substrate, the substrate further including a first trench the first trench formed outside a side of the gate; first and second doped regions, formed in the substrate, the first and second doped regions formed on two sides of the gate, the first trench formed between the gate and the first doped region; and first and second lightly-doped drain (LDD) regions, formed in the substrate. The first LDD region is formed between the first trench and the first doped region. The second LDD region is formed between the gate and the second doped region. The first and second doped regions form a source and a drain, respectively. The first trench is deeper than the first and the second lightly-doped drain regions.

Abstract: To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first bump on the first region and a second bump on the second region; forming a first doped layer on the first fin-shaped structure and the first bump; and forming a second doped layer on the second fin-shaped structure and the second bump.

Abstract: A first channel structure includes SixGe1-x and a second channel structure includes a group III-V compound material. First and second gate stacks are formed on the first and second channel structures. An insulating layer is formed on the gate stacks and the channel structures and is removed from the first channel structure to form a spacer on sidewalls of the first gate stack. First raised source and drain layers are formed on the first channel structure. The insulating layer is removed from the second channel structure to form a spacer on sidewalls of the second gate stack. The surfaces of the first and second channel structures and first source and drain layers are oxidized. The oxide layers are treated by a cleaning process that selectively removes the second native oxide layer only. Second raised source and drain layers are formed on the second channel structure. A CMOS structure is disclosed.

Abstract: A device and method for localizing underfill includes a substrate, a plurality of dies, and underfill material. The substrate includes a plurality of contacts and a plurality of cavities separated by a plurality of mesas. The plurality of dies is mounted to the substrate using the plurality of contacts. The underfill material is located between the substrate and the dies. The underfill material is localized into a plurality of regions using the mesas. Each of the contacts is located in a respective one of the cavities. In some embodiments, the substrate further includes a plurality of channels interconnecting the cavities. In some embodiments, the substrate further includes a plurality of intra-cavity mesas for further localizing the underfill material. In some embodiments, outer edges of a first one of the dies rest on first mesas located on edges of a first one of the cavities.

Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

Abstract: A display device includes a transistor including first and second gates. A first terminal of the transistor is electrically connected to a third wiring. A first switch controls electrical connection between a first wiring and the first gate. A second switch controls electrical connection between a second wiring and the second gate. A third switch controls electrical connection between the first gate and a second terminal of the transistor. A fourth switch controls electrical connection between a fifth wiring and the second terminal of the transistor. A first capacitor retains a potential difference between the first gate and the second terminal of the transistor. A second capacitor retains a potential difference between the first gate and the second gate. A first terminal of the light-emitting element is electrically connected to the second terminal of the transistor. A second terminal of the light-emitting element is electrically connected to a fourth wiring.

Abstract: A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract: An organic electroluminescent display device includes a first substrate having a pixel area including a plurality of pixels each including a plurality of sub pixels, a light emitting devices are provided in correspondence with the sub pixels, and a partition layer covering a peripheral portion of each of the sub pixels; and a second substrate having a sensing unit including a first electrode pattern extending in one direction and a second electrode pattern extending in a direction intersecting the one direction, and the first electrode pattern and the second electrode pattern is provided out of contact from each other. The first electrode pattern is located to overlap the partition layer so as to enclose the sub pixels. The first electrode pattern included in the sensing unit encloses the sub pixels, and thus light is prevented from leaking to adjacent sub pixels.

Abstract: A display device includes a gate line and a data line on a first substrate. A first passivation layer disposed thereon has a first contact hole. A second passivation layer on the first passivation layer has a second contact hole. A common electrode is disposed on the second passivation layer and a residual pattern is disposed on a drain electrode. A third passivation layer, having a third contact hole, is disposed on the common electrode. A pixel electrode, connected to the drain electrode, is disposed on the third passivation layer. A groove is defined between the first and second passivation layers. The common electrode has a open circuit from the residual pattern thereof.

Abstract: Devices and method related to stacked duplexers. In some embodiments, an assembly may include a first wafer-level packaging (WLP) device having a radio-frequency (RF) shield. The assembly may also include a second WLP device having an RF shield, the second WLP device positioned over the first WLP device such that the RF shield of the second WLP device is electrically connected to the RF shield of the first WLP device.

Abstract: A layer of an interconnect structure is formed over a substrate. The layer contains an interlayer dielectric (ILD) material and a metal line disposed in the ILD. A first etching stop layer is formed on the ILD but not on the metal line. The first etching stop layer is formed through a selective atomic layer deposition (ALD) process. A second etching stop layer is formed over the first etching stop layer. A high etching selectivity exists between the first and second etching stop layers. A via is formed to be at least partially aligned with, and electrically coupled to, the metal line. The first etching stop layer prevents the ILD from being etched through during the formation of the via.

Abstract: Semiconductor devices are provided. The semiconductor device includes a first fin portion and a second fin portion arranged on a substrate and extended in a first direction, the first fin portion and the second fin portion being spaced apart from each other in the first direction, a field insulating layer between the first fin portion and the second fin portion and having an upper surface thereof lower than an upper surface of the first fin portion, a first metal gate extended in a second direction on the first fin portion and a silicon gate extended in the second direction on the field insulating layer and contacting the field insulating layer.