Abstract: An electronic component comprises: a resin frame; a semiconductor substrate housed in the resin frame; a plate shape metal member having at least one end fixed in the resin frame at a position spaced apart from the semiconductor substrate; an electrical connection region portion formed on the surface on the side of the plate shape metal member of the semiconductor substrate with an electrically conductive material; and a solder layer formed on the surface on the side of the plate shape metal member of the electrical connection region portion, wherein the plate shape metal member supports the semiconductor substrate without contact through the solder layer and the electrical connection region portion, and is electrically connected to the electrical connection region portion.

Abstract: A method of fabricating a semiconductor device includes: providing a semiconductor substrate including a hard mask layer; performing, using the hard mask layer, etching to the semiconductor substrate to form a fin-type structure and a groove; forming an isolation material layer in the regions between adjacent fins of the fin-type structure and in the groove; removing a portion of the isolation material layer that is located above the hard mask layer to form a shallow trench isolation; and forming a second mask layer over the hard mask layer, the second mask layer having an opening above the shallow trench isolation; performing ion implantation to the shallow trench isolation through the opening; removing the second mask layer and the hard mask layer; and removing a portion of the isolation material layer located in the regions between adjacent fins of the fin-type structure and a portion of the shallow trench isolation.

Abstract: Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.

Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.

Abstract: An embodiment method includes providing a carrier having a recess and attaching a die to the carrier, wherein the die is at least partially disposed in the recess. The method further includes forming a molding compound over the carrier and around at least a portion of the die, forming fan-out redistribution layers over the molding compound and electrically connected to the die, and removing the carrier.

Abstract: A semiconductor package includes an output inductor placed over a support substrate, a power semiconductor die having a bottom surface situated on the support substrate and a top surface having an active region, where the output inductor is coupled to the active region on the top surface of the support substrate, and where the support substrate includes a plurality of bar vias. The output inductor is a packaged component having at least two leads in electrical connection with the active region of the power semiconductor die. The support substrate further includes routing conductors in electrical connection with the active region of the power semiconductor die. The power semiconductor die includes a control transistor and a sync transistor connected in a half-bridge.

Abstract: An optoelectronic semiconductor component includes a layer stack based on a nitride compound semiconductor and has an n-type semiconductor region , a p-type semiconductor region and an active layer arranged between the n-type semiconductor region and the p-type semiconductor region. In order to form an electron barrier, the p-type semiconductor region includes a layer sequence having a plurality of p-doped layers composed of AlxInyGa1?x?yN where 0<=x<=1, 0<=y<=1 and x+y<=1. The layer sequence includes a first p-doped layer having an aluminum proportion x1>=0.5 and a thickness of not more than 3 nm, and the first p-doped layer, at a side facing away from the active layer, is succeeded by at least a second p-doped layer having an aluminum proportion x2<x1 and a third p-doped layer having an aluminum proportion x3<x2.

Abstract: Some features pertain to an integrated device that include a first integrated circuit (IC) package comprising a first laminated substrate, a flexible connector coupled to the first laminated substrate, and a second integrated circuit (IC) package comprising a second laminated substrate. The second laminated substrate is coupled to the flexible connector. The flexible connector includes a dielectric layer and an interconnect. The dielectric layer and the interconnect substantially extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer and the interconnect of the flexible connector, contiguously extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer extends into a substantial portion of the first laminated substrate. In some implementations, the dielectric layer includes polyimide (PI) layer.

Abstract: A display device includes an element substrate including a display area where a plurality of self-light-emitting elements are formed, and a driver IC disposed outside the display area in the element substrate. A first metal layer is disposed on the reverse side of the element substrate at a position opposite to the display area. A second metal layer is disposed with a space between the first metal layer and the second metal layer on the reverse side of the element substrate at a position opposite to the driver IC.

Abstract: Fin-type transistor fabrication methods and structures are provided which include, for example, providing a gate structure extending at least partially over a fin extended above a substrate structure, the gate structure being disposed adjacent to at least one region of the fin; disposing a protective film conformally over the gate structure and over the at least one region; modifying the protective film over the at least one region of the fin to form a conformal buffer layer, wherein the modifying selectively alters a crystalline structure of the protective film over the at least one region which thereby becomes the conformal buffer layer, without altering the crystalline structure of the protective film disposed over the gate structure; and removing the un-altered protective film over the gate structure, leaving the conformal buffer layer over the at least one region to form a source region and a drain region of the fin-type transistor.

Abstract: A solid-state radiation detector comprising a photosensitive sensor comprises photosensitive elements that are organized in a matrix, and a light generator whose purpose is to optically wipe the photosensitive elements. The light generator comprises: an electroluminescent layer that is distributed over the surface of the sensor; at least one electrode that continuously covers the electroluminescent layer and in which electrons may flow, the light emitted by the electroluminescent layer being capable of passing through the electrode; and additional electrical conductors that are in electrical contact with the electrode, the additional electrical conductors forming branches that extend over the surface of the electrode, and being spatially distributed across the surface of the electrode.

Abstract: The present disclosure provides a semiconductor package, including a semiconductor die and a substrate having a first surface electrically coupled to the semiconductor die and a second surface opposing to the first surface. The first surface includes a core region having a plurality of landing pads and a periphery region surrounding the core region and having a plurality of landing traces. A pitch of the landing pads is from about 55 ?m to about 280 ?m. The semiconductor die includes a third surface facing the first surface of the substrate and a fourth surface opposing to the third surface. The third surface includes a plurality of elongated bump positioned correspondingly to the landing pads and the landing traces of the substrate, and the elongated bump includes a long axis and a short axis perpendicular to the long axis on a cross section thereof.

Abstract: Some features pertain to an integrated device that includes a first integrated circuit (IC) package, a flexible connector and a second integrated circuit (IC) package. The first integrated circuit (IC) package includes a first die, a plurality of first interconnects, and a first dielectric layer encapsulating the first die. The flexible connector is coupled to the first integrated circuit (IC) package. The flexible connector includes the first dielectric layer, and an interconnect. The second integrated circuit (IC) package is coupled to the flexible connector. The second integrated circuit (IC) package includes the first dielectric layer, and a plurality of second interconnects. The first integrated circuit (IC) package, the second integrated circuit (IC) package, and the flexible connector are coupled together through at least a portion (e.g., contiguous portion) of the first dielectric layer. In some implementations, the flexible connector comprises a dummy metal layer.

Abstract: A semiconductor structure includes a substrate, a source/drain (S/D) junction, and an S/D contact. The S/D junction is associated with the substrate and includes a trench-defining wall, a semiconductor layer, and a semiconductor material. The trench-defining wall defines a trench. The semiconductor layer is formed over the trench-defining wall, partially fills the trench, substantially covers the trench-defining wall, and includes germanium. The semiconductor material is formed over the semiconductor layer and includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer. The S/D contact is formed over the S/D junction.

Abstract: A semiconductor device (100) comprising a leadframe with a pad (101) and elongated leads (103) made of a base metal plated with a layer enabling metal-to-metal bonding; a semiconductor chip (110) attached to the pad, the chip having terminals. A metallic wire connection (130) from a terminal to a respective lead, the connection including a first ball bond by a first squashed ball (131) attached to the terminal, and a first stitch bond (132) attached to the lead. A second squashed ball (150) of the wire metal attached to the lead as a second ball bond adjacent to the first stitch bond (132). A package (170) of a polymeric compound encapsulating the chip, wire connection, second ball and at least a portion of the elongated lead, the compound adhering to the materials of the encapsulated entities.

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

Abstract: FinFET devices and methods of forming the same are disclosed. One FinFET device includes a substrate with first and second fins in a first region and third and fourth fins in a second region, and first to fourth gates respectively across the first to fourth fins. The first end sidewall of the first gate is faced to the second end sidewall of the second gate, and a first opening is formed between the first and second end sidewalls. The third end sidewall of the third gate is faced to the fourth end sidewall of the fourth gate, and a second opening is formed between the third and fourth end sidewalls. The first and second regions have different pattern densities, and the included angle between the sidewall of the first opening and the substrate is different from the included angle between the sidewall of the second opening and the substrate.

Abstract: A semiconductor device includes a plurality of semiconductor dies stacked vertically to have a vertical height and a dielectric surrounding the stacked semiconductor dies. The semiconductor device further has a conductive post external to the stacked semiconductor dies and extending through the dielectric. In the semiconductor device, a height of the conductive post is greater than the vertical height.

Abstract: A multichip package includes a first semiconductor device mounted on a first leadframe, in which a primary heat producing surface of the first semiconductor device is oriented towards and in contact with a heat dispersing region of the first leadframe. A second semiconductor device is mounted on a second leadframe, in which a primary heat producing surface of the second semiconductor device is oriented towards and in contact with a heat dispersing region of the second leadframe. A surface of the heat dispersing region of the first leadframe is exposed on a first side of the multichip package, and a surface of the heat dispersing region of the second leadframe is exposed on a second side of the multichip package that is opposite from the first side.

Abstract: A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.