Abstract: Described is a linear and symmetric time-to-digital converter (TDC) which comprises: a first input; a second input; a first delay line having a plurality of delay stages coupled together in series, the first delay line to receive the first input; a second delay line having a plurality of delay stages coupled together in series, the second delay line to receive the second input; and a plurality of comparators, each having first and second outputs coupled to the first and second delay lines.

Abstract: A clock signal generator includes a quartz crystal multivibrator circuit and a pulse-shaping circuit. The pulse-shaping circuit includes a D trigger. The D trigger includes a Q terminal, a Q? terminal, a CP terminal, and a D terminal. An output signal from the quartz crystal multivibrator is transferred to the CP terminal. The Q? terminal is connected to the D terminal. The Q terminal is an output end of the clock signal. A capacitor C4 is connected between the CP terminal and ground. A capacitor C5 is connected between the D terminal and ground. The capacitance of the capacitors C4 and C5 is adjusted to attain a clock signal of a predetermined frequency.

Abstract: A timing domain crossing apparatus and method of transferring signals between timing domains are disclosed. A receiver samples a data signal with a sample clock in a first timing domain. The sampled data signal is expanded to a plurality of expansion signals, which are held valid for a plurality of consecutive active clock cycles. A data order adjuster may re-order the plurality of expansion signals to a predetermined order. A timing generator samples a command signal with an internal clock in a second timing domain to generate a re-timing strobe. The re-timing strobe may be temporally positioned to be within the expansion data window and used to sample the plurality of expansion signals in the second timing domain. The timing domain crossing apparatus and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.

Abstract: A switching circuit includes a semiconductor switching element having a control electrode and a source-drain current path, the source-drain current path being connected between a voltage source and a load circuit, a parallel circuit formed by first and second transistors having respective collector-emitter paths connected between the control electrode of the semiconductor switching element and a reference potential point, a first resistor connected to the second transistor in series, a differential circuit connected between a control signal terminal and the base of the first transistor and a second resistor connected between the control signal terminal and the base of the second transistor. The first transistor is made conductive by a signal obtained by differentiating a control signal and subsequently the second transistor is made conductive to control the semiconductor switching element for ON/OFF.

Abstract: Hysteresis circuit 10 is composed of three inverters 40, 42, 44. Node NB in hysteresis circuit 10 is connected to the input terminal of transition-detecting part 14 of transmission control part 12. Transition-detecting part 14 detects the timing of the start of the output inversion operation and the timing of the completion of the transition in hysteresis circuit 10 corresponding to potential VB of node NB, and it controls activation/deactivation of inverter 50 on the signal transmission path.

Abstract: A phase adjustment circuit generates multiple clock signals by, for example, successively delaying a first clock signal. One of the generated clock signals is selected and output. A phase difference detector determines whether the phase of the selected clock signal and the phase of a second clock signal satisfy a given condition. The clock signal selection can changed until the condition is satisfied, either by external control by a device that monitors a signal output by the phase difference detector, or by a built-in selection signal generator. This scheme assures that two clock signals with phases satisfying the given condition are obtained, regardless of environmental factors or fabrication variations.

Abstract: A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows maximum tracking bandwidth, regardless of process, voltage, or temperature variations. Central to the technique is to effectively operate the loop at a lower frequency close to its own intrinsic bandwidth (1/tLoop) instead of at the higher frequency of the clock signal (1/tCK). To do so, in one embodiment, the loop delay, tLoop, is measured or estimated prior to operation of the loop. The phase detector is then enabled to operate close to the loop frequency, 1/tLoop. In short, the phase detector is made not to see activity during useless delay times, which prevents the loop from overreacting and becoming unstable.

Abstract: Systems and techniques for producing a signal with a known phase relationship to a source clock at an output of an indeterminate circuit element such as a clock divider. The systems and techniques may be used to allow circuit test data to be accurately compared with simulation data.

Abstract: A duty cycle corrector including a restore circuit configured to receive a differential input clock and a differential feedback clock each having crossings of a first type and a second type and to provide a differential output clock having crossing of the first type based on differential input clock crossings of the first type and crossings of the second type based on differential feedback clock crossings of the first type. A delay element configured to delay the differential output clock by a delay time to provide the differential feedback clock. An adjuster circuit configured to receive the differential input and feedback clocks and to adjust the delay time so as to maintain a duty cycle of the differential output clock substantially at a desired duty cycle.

Abstract: A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The master and slave transparent latches have opposite transparent polarities when in a functional mode and have the same polarities (e.g., positive level sense) when in a scan mode. The transparent polarity of a transparent latch defines the state of a clock to that latch for which the transparent latch is transparent.

Abstract: First and second analog switches are connected in series between first and second nodes. One terminal of a third analog switch is connected to a series connection node of the first and second analog switches. The other terminal of the third analog switch is supplied with a second voltage different from a first voltage applied to the first node. The third analog switch drives on when the first and second analog switches drive off, and outputs the second voltage to the series connection node of the first and second analog switches.

Abstract: A circuit arrangement for bidirectional current limiting comprises a first transistor, a second transistor, a first resistor, a first zener diode and a second zener diode. The first transistor comprises a first controllable path and a first control terminal and the second transistor comprises a second controllable path and a second control terminal. The first and the second control terminals are connected to a first current source and the first resistor is connected between the first and the second controllable paths. The first zener diode is connected between the first current source and a first line node which is located between the first controllable path of the first transistor and the first resistor. The second zener diode is connected between the first current source and a second line node which is located between the second controllable path of the second transistor and the first resistor.

Abstract: A differential sense amplifier is described that can be configured as a preamplifier or a latch circuit as triggered by a clock signal connected to a switch circuit. When the clock signal is set at a first signal level, the switch circuit in the differential sense amplifier is activated so that the differential sense amplifier is configured as a preamplifier with a positive feedback circuit. When the clock signal is set at a second signal level, the switch circuit in the differential sense amplifier is deactivated so that the differential sense amplifier is configured as the latch circuit. For one read cycle, the differential sense amplifier operates first as the preamplifier and then as the latch circuit.

Abstract: A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked ioop generating one or more delayed periodic signals and a control signal for controlling the time delay between the periodic input signal and the delayed periodic signals. The delay circuit also includes a controlled delay circuit for generating one or more delayed periodic signals. The controlled delay circuit has an input terminal for receiving at least one of the delayed periodic signals from the delay locked loop and a delay control terminal coupled to the control signal from the delay locked ioop for controlling the time delay between the delayed periodic input signal received from the delay locked loop and the one or more delayed periodic signals generated by the controlled delay circuit.

Abstract: A comparator has first and second current paths, each passing from an input through a transistor, through a current source to ground, the second current path also having a reference voltage drop element coupled in series with the second input. The gates of the transistors are coupled to form a current mirror. The reference voltage drop element enables higher voltages to be input and compared to higher thresholds above an internal supply voltage level without the need for dividing resistors to reduce the input voltage. Avoiding such resistors means the power dissipation and the silicon area used can be kept lower. ESD vulnerability is reduced since the inputs are not coupled to gates of MOS transistors. Overvoltage protection across the source and gate of the second transistor can be added.

Abstract: A high voltage-generating circuit comprises a control circuit for generating a control signal for executing an operation command and generating a refresh signal depending upon a refresh operation, an oscillator driven according to an enable signal, for outputting an oscillation signal the cycle of which is controlled according to a refresh signal, a charge pump circuit for generating a high voltage using a power source voltage according to the oscillation signal, wherein the charge pump circuit has the ascent rate of the high voltage controlled according to variation in the cycle of the oscillation signal, and a level detection circuit for comparing the high voltage and a reference voltage to determine whether the high voltage reaches a target value, and controlling the operation of the oscillator according to the result of the comparison.

Abstract: A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first transistor also is coupled to a voltage source. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports, a slave feedback loop and a second transistor coupled to the slave feedback loop. The second transistor is coupled to the voltage source or a different voltage source. When a clock signal is in a first state, the first single transistor is activated to reset the digital storage element. When the clock signal is in a second state, the second single transistor is activated to reset the digital storage element.

Abstract: A step-down voltage output circuit preventing: latch-up phenomenon in a load circuit for a period between a power-supply activation and complete start of a charge pump circuit; and rapid change of a substrate potential when a step-down voltage output is changed from ON to OFF. The step-down voltage output circuit has a timer circuit that operates depending on control signals and a timer period; a first N-channel MOS transistor in which a source is connected to a step-down voltage output terminal, a drain is connected to ground, a gate is connected to a power-supply voltage input terminal through a resistance; and a second N-channel MOS transistor in which a source is connected to the step-down voltage output terminal, a drain is connected to the gate of the first N-channel MOS transistor, and a gate is connected to an output terminal of the timer circuit.

Abstract: Provided is a temperature-compensated circuit for a power amplifier through diode voltage control, in which a first resistor (Rref), a first diode (D1), and a second diode (D2) are connected to a reference voltage in series. The temperature-compensated circuit includes a second resistor (R1) connected to the reference voltage, a third resistor (R2) connected to the second resistor in series, a fourth resistor (Rc) having one terminal connected to the reference voltage, a fifth resistor (Re) having one terminal connected to ground, a bias transistor having a base terminal connected to a contact point (VS) between the second resistor and the third resistor, a collector terminal connected to the other terminal of the fourth resistor, and an emitter terminal connected to the other terminal of the fifth resistor, and a sixth resistor (Rf) connected between a series connection terminal between the first diode and the second diode, and the collector terminal of the bias transistor.

Abstract: A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in response to charge flow that is regulated by the first circuit and the second circuit, wherein the first circuit is configured to receive a clock signal and change the charge flow at a first transition of the clock signal. The second circuit is configured to change the charge flow at a second transition of the clock signal. The first circuit and the second circuit are configured to change the charge flow in response to obtaining the threshold value.