Abstract: A buffer circuit includes a first transistor (T1) having a base connected to a first power supply, the emitter (E1) and collector (C1) connected as input and output nodes, a second transistor (T2) having a base connected to the first power supply, a first constant current circuit using a difference between outgoing current from E1 and an input current at the current signal input node as a constant current, and determining outgoing current from the emitter of T2 equal to the constant current; and a first mirror circuit equalizing first and second collector currents with a third transistor (T3) with C1 and a fourth transistor (T4) with a collector connected to a collector of T2, a first operating point voltage is provided to the current signal output node between T3 and T1, and a second operating point voltage based on the first operating point voltage between T4 and T2.

Abstract: A technique for increasing the charge storage capacity of a charge storage device without changing its inherent charge transfer function. The technique may be used to implement a charge domain signal processing circuits such as Analog to Digital Converters (ADCs) used in digital radio frequency signal receivers.

Abstract: Disclosed herein is an apparatus for outputting complementary signals using bootstrapping technology. The apparatus for outputting complementary signals includes a precharaged logic block, one or more output nodes, and a bootstrapping circuit block. The precharged differential logic block generates a differential signal depending on an input signal. The one or more output nodes output the complementary signals depending on the differential signal. The bootstrapping circuit block is shared by the one or more output nodes, and amplifies the complementary signals.

Abstract: An ECU has a main IC and at least one auxiliary IC, with at least the auxiliary IC driving one or more MOS FETs to control supplying of power to respective electrical loads, e.g., in a vehicle. A stepped-up voltage, higher than the circuit power source voltage, is generated within the main IC and supplied to each auxiliary IC, for driving gate electrodes of the MOS FETs. Electrical noise produced by operation of a voltage step-up circuit in the main IC is effectively suppressed by elements that are coupled only to a power source terminal of the main IC alone.

Abstract: A simple, low cost circuit with only passive components, and thus low power consumption, is provided for baseline restoration of an AC coupled signal. The circuit includes a passive network of diodes arranged in a star configuration and an RF-transformer. A differential signal strategy may be employed by including a differential amplifier at the input and output of the passive network.

Abstract: A PLL-based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The system may include two primary functional blocks—an input PLL with its reference path containing an integer divider coupled with a SDM (a fractional frequency divider), and an output PLL with its feedback path containing an integer divider coupled with a SDM (a fractional frequency multiplier). The combination of an integer divider and an SDM yields a fractional divider that divides by N+F/M, where N is the integer portion of the division and F/M is the fractional portion of the division, with M denoting the fractional modulus. Furthermore, since it is desirable to have programmable division factors, it is beneficial to define N, F and M as integers as this simplifies a programming interface when the frequency translator is manufactured as an integrated circuit.

Abstract: A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

Abstract: A voltage trimming circuit is provided. The voltage trimming circuit has an input stage, an up-trimming resistor ladder, a down-trimming resistor ladder and a control means. The input stage has a first input, a second input and an output, wherein the first output is to receive an input voltage, the second input is connected to a connection point and the output is to provide an output voltage based on a difference between the voltage of the first and the second input. The up-trimming resistor ladder is connected between the output of the input stage and the connection point and the down-trimming resistor ladder connected between a ground potential and the connection point. The control means controls the resistance of the up-trimming and the down-trimming resistor ladder to up-trim or down-trim the output voltage.

Abstract: A switching circuit configured to reduce the effects of signal oscillation on the operation of the switching circuit is provided. The switching circuit may include signal oscillation and detection circuitry that suppresses control signals during a detected oscillation, allowing stored energy to naturally decay in the switching circuit and thereby prevent unwanted extension of the oscillation that may be caused by the repeated switching of a semiconductor element coupled between the input and output of the switching circuit.

Abstract: A method of dealing with anomalies in an output signal is provided. The method includes monitoring transitions in the output signal. When transitions do not occur at expected times, detecting an anomalous signal. Determining the type of anomalous signal based at least in part on the time period of the anomalous signal and conditioning the output signal based on the type of anomalous signal detected.

Abstract: Circuit, system and method of current control circuits are disclosed. In one embodiment, a control circuit includes a first MOS transistor and a second MOS transistor. The first source/drains of the first and the second MOS transistors are coupled to an output of a power source. A second source/drain of the first MOS transistor is coupled to a first output node of the current control circuit. A second source/drain of the second MOS transistor is coupled to a second output node of the current control circuit. The control circuit further includes a means to block flow of current from the first output node of the current control circuit to the second output node of the current control circuit.

Abstract: There is provided a signal generating apparatus for generating an output signal corresponding to pattern data supplied thereto. The signal generating apparatus includes a timing generating section that generates a periodic signal, a shift register section including a plurality of flip-flops in a cascade arrangement through which each piece of data of the pattern data is propagated sequentially in response to the periodic signal, a waveform generating section that generates the output signal whose value varies in accordance with a cycle of the periodic signal, based on data values output from the plurality of flip-flops, and an analog circuit that enhances a predetermined frequency component in a waveform of the output signal generated by the waveform generating section.

Abstract: The present invention is applicable to an electronic device including a master, a slave, a bus coupling the master and the slave and a clock generator for providing a system clock to the master and slave. The clock generator determines whether the received data is correct on a cycle-by-cycle basis. The clock generator suppresses an edge of a next clock cycle of the system clock signal if the data is not to be correct. The clock generator allows the edge of a next clock cycle of the system clock signal if the data is correct.

Abstract: A circuit adapting pin output levels to a reference level in which a digital comparator compares an output voltage from an output pin of a device to a reference voltage level. The comparator, relying on the polarity of the comparator output as well as the registered polarity of the comparator output on the previous clock cycle, signals a state machine, which sends a clocked signal to a sense circuit and voltage regulator. The sense circuit may modify a resistance in a switched resistor network, such that the output level is incrementally stepped at clocked intervals towards the reference voltage until the polarity of the error signal reverses. When the output voltage crosses the reference voltage threshold, the comparator flips states and continues to regulate output pin voltage to the reference voltage level.

Abstract: A High-Definition Multimedia Interface (HDMI) cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: There is provided a signal processing apparatus including a variable capacitor and a switching portion for switching the circuit mode between a sampling mode, in which the variable capacitor samples an input signal, a holding mode, in which a charge gained by sampling the input signal is held in the variable capacitor, and an output mode for outputting the charge stored in the variable capacitor, wherein the variable capacitor is provided with an input terminal through which the input signal is inputted in the sampling mode, a control terminal to which a first control signal which decreases the capacitance of the variable capacitor to a value below the capacitance in the sampling mode is inputted in the output mode, and a second control signal having a predetermined reference voltage is inputted in the holding mode, where an insulating layer is provided between the control terminal and the input terminal.

Abstract: A circuit for generating negative voltage includes a variable period oscillator configured to generate an oscillator signal enabled in response to a detection signal and to determine a period of the oscillator signal in response to a control signal, a pump configured to perform pumping operations in response to the oscillator signal and to generate a negative voltage by the pumping operations, a negative voltage detecting unit configured to detect the level of the negative voltage to generate the detection signal, and a gate-induced drain leakage current detecting unit configured to measure the amount of a gate-induced drain leakage current to generate the control signal.

Abstract: A driver is provided. The driver generally comprises a current source, a current mirror, an amplifier and a presetting circuit. The current source is generally adapted to provide a reference current to the current mirror. The transistor is coupled to the current mirror. The amplifier has the first input that is coupled to the current mirror, a second input that is coupled to a node between the transistor and the current mirror, and an output that is coupled to the control electrode of the transistor. The presetting circuit is coupled to the control electrode of the transistor so that it can preset the potential of the control electrode of the transistor to a potential that allows current driving of the transistor with a predetermined timing after a control signal is received.

Abstract: A dynamic flip-flop includes first and second input stages forming a differential input stage adapted to receive differential data. The flip-flop is reset in response to a reset signal. To ensure proper operation, a transistor disposed between the first and second input stages is always maintained active to provide a conduction path between the ground terminal and the nodes that may be charged from the supply voltage. To improve the setup and hold time of the flip-flop, the clock signal is applied to a first transistor disposed in the first input stage and a second transistor disposed in the second input stage.

Abstract: An electronic device for delivering DC power includes a load, a power end, an upper gate switch including a first end coupled to the power, a second end, and a third end, for conducting connection between the first and third ends according to the signal level of the second end, a lower gate switch including a first end coupled to the third end of the upper gate switch, a second end, and a third end coupled to ground, for conducting connection between the first and third ends according to the signal level of the second end, an inductor, and a switch control unit, coupled to the second end of the upper gate switch and the second end of the lower gate switch, for switching the upper gate switch between an ON state and an OFF state, and switching the lower gate switch between an ON state and a semi-ON state.