Abstract: In one embodiment, a phase detector is provided comprising a first input, a second input, and first circuitry in communication with the first and second inputs, the first circuitry operative to provide an indication of a phase difference between a first signal supplied by the first input and a second signal supplied by the second input, wherein an aberration in one of the first and second signals results in an incorrect indication of phase difference. The phase detector also comprises second circuitry in communication with the first circuitry, the second circuitry operative to provide a correct indication of phase difference despite the aberration in the at least one of the first and second signals. In another embodiment, a differential phase detector is provided.

Abstract: An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node ‘Vcmi’. An alternative, switched-capacitor-based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.

Abstract: The purpose of the present invention is to decrease a leak current of a voltage supply circuit using a MOS transistor. This voltage supply circuit comprises an n-channel MOS transistor having a low threshold voltage, the drain of which is connected to the power supply voltage, and a p-channel MOS transistor, the source of which is connected to the source of the n-channel MOS transistor and which supplies a voltage vii from the drain to a load circuit. Since a voltage V gs=1 V is applied to the gate-sources of the p-channel MOS transistor when said circuit is on standby, the p-channel MOS transistor operates in a larger cut-off region than an ordinary cut-off region.

Abstract: A dynamic flip-flop includes a leakage compensation circuit enabling operation over a wide range of frequencies. Nodes of the dynamic flip-flop store the flip-flop's state. The leakage compensation circuit drains leakage currents from these nodes to prevent the node voltage from rising and triggering an erroneous state change when a data signal changes in the middle of the clock cycle. The leakage compensation circuit associated with a node is activated when the node is set to a low logic level voltage. The leakage compensation circuit is adapted to draw a current from a node that compensates for the leakage current supplied to the node. At the least, this current draw is sufficient to prevent the voltage at the node from rising above a state change threshold voltage during the time period between refresh operations.

Abstract: In various embodiments, an apparatus for down-converting a first signal having a first frequency to a lower frequency is disclosed. The apparatus can include one or more arrays of N over-damped, bi-stable circuits unidirectionally-coupled from element to element.

Abstract: A temperature sensing circuit using a delay locked loop and a temperature sensing method. The temperature sensing circuit includes a locked delay unit for receiving an external clock and generating a locked delay pulse keeping a constant delay amount regardless of temperature. A variable delay unit may have a chain structure of a plurality of delay cells depending upon temperature. The variable delay unit may receive the external clock and generate variable delay pulses having respectively different delay amounts based on temperature. A decision control unit is configured to sense a determination temperature by using a phase difference between one selected from the variable delay pulses and the locked delay pulse. Accordingly, an unnecessary time and cost causable by temperature compensation can be reduced, and an automatic temperature compensation and a precise temperature sensing operation can be obtained.

Abstract: For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.

Abstract: A device for driving switching elements is provided with a potential detector 29 which provides drive circuit 30 with signals in response to differences among potentials at junctions 17 to 20 of first and third resistors 13, 15, third resistor 15 and first control MOS-FET 8, second and fourth resistors 14, 16 and fourth resistor 16 and second control MOS-FET 9 so that drive circuit 30 supplies drive signals to a gate terminal of a first MOS-FET 1 based on potentials in first and second series circuits 11 and 12. When appropriate resistance values are selected for first to fourth resistors 13 to 16, potential detector 29 precisely detects the potential at each junction 17 to 20 to produce detection signals and prevent malfunction of drive circuit 30 even upon occurrence of abnormal signals or noises resulted from abrupt potential rise.

Abstract: A circuit arrangement for generating an IQ signal which comprises an oscillator (3) and a frequency divider (4). The oscillator (3) and the frequency divider (4) are arranged in a common current path between the supply and reference potentials (7, 5) in accordance with the proposed principle. It is possible to operate the two function blocks using a common BIAS current and additionally to save components.

Abstract: A system and method for performing phase-locked loop is disclosed. The system includes phase frequency detector circuitry, charge pump circuitry having first current mirror circuitry and second current mirror circuitry, loop filter circuitry, and voltage controlled oscillator circuitry. The phase frequency detector circuitry generates an up signal and a down signal based on the phase difference of an input signal and a feedback signal. The charge pump circuitry includes the first current mirror circuitry and the second mirror circuitry and generates a charge pump output signal based on the up and down signals. The loop filter circuitry generates a filtered control signal based on the charge pump output signal. The voltage controlled oscillator circuitry generates the feedback signal with a repeating waveform based on the filtered control signal.

Abstract: A plurality of flip-flop circuits, having different circuit configurations, which perform an identical digital signal processing are mixed on a single semiconductor substrate. A first flip-flop circuit among the plurality of flip-flop circuits receives a clock signal supplied from outside the flip-flop circuits, through at least two stage inverters, and operates with clock signals outputted from the inverters. A second flip-flop circuit receives the clock signal supplied from outside the flip-flop circuits through at least one inverter having a less number of stages than the number of stages of the inverter contained in the first flip-flop circuit, and operates with at least one of the clock signal and a clock signal outputted from the inverter.

Abstract: A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.

Abstract: A logarithmic linear variable gain CMOS amplifier includes first and second differential pairs of transistors forming a differential input, with each differential pair of transistors including a common source node. A pair of diode-connected load transistors is connected to the first and second differential pairs of transistors, and a third differential pair of transistors is connected to the pair of diode-connected load transistors. The third differential pair of transistors include respective gates connected together and in parallel to gates of the first and second differential pairs of transistors. First and second current mirrors are respectively connected to the common source nodes of the first and second differential pairs of transistors for programmably injecting respective bias currents thereto, with a sum of the respective bias currents remaining constant.

Abstract: A drive circuit for driving a voltage-driven-type element including a gate terminal, an emitter terminal and a collector terminal includes a first semiconductor switch including an output terminal disposed between a power source for the drive circuit and the gate terminal, a first resistor disposed between the output terminal and the gate terminal and a capacitive element connected in parallel with the first semiconductor switch. The capacitive element supplies an external electric charge from the power source to a portion between the gate terminal and the emitter terminal after an internal electric charge accumulated in the portion between the gate terminal and the emitter terminal is supplied to a portion between the gate terminal and the collector terminal.

Abstract: An integrated circuit including a first circuit block having a power supply terminal for receiving a first power supply voltage and an output terminal for providing a first data signal is provided. The integrated circuit further includes a second circuit block having a power supply voltage terminal for receiving a second power supply voltage and an input terminal coupled to the output terminal of the first circuit block for receiving the first data signal. The integrated circuit further includes a first programmable delay block for adding a first delay time to the first data signal when one or both of the first or second power supply voltages is changed.

Abstract: The present invention provides an integrated virtual voltage circuit for use with a sub-circuit. In one embodiment, the integrated virtual voltage circuit includes a MOS transistor switch coupled to a supply voltage and configured to employ a drain to provide an operating voltage for the sub-circuit during switch activation. Additionally, the integrated virtual voltage circuit also includes a connection unit coupled to the MOS transistor switch and configured to provide a standby voltage for the sub-circuit during deactivation of the MOS transistor switch wherein the standby voltage is based on a static coupling of the drain to a body region of the MOS transistor switch. In an alternative embodiment, the connection unit is further configured to connect a voltage reference between the supply voltage and the drain of the MOS transistor switch to determine the standby voltage.

Abstract: A programmable gain attenuator (PGA) in particular to be used in a track-and-hold circuit is disclosed. The PGA is located in the feedback path around an operational amplifier. One tap switch is used to connect one PGA section to the output of the operational amplifier. The PGA section is capable of producing a multiplicity of different gain settings by using a multiplicity of secondary resistive devices in a voltage divider, wherein the resistive devices each can be independently coupled to a reference voltage.

Abstract: A high voltage generator includes: a detection unit for comparing a reference voltage with a high voltage and detecting a voltage level of the high voltage; an oscillator selection unit for generating a first control signal and a second control signal in response to an output signal of the detection unit and a selection signal corresponding to a data operation mode; an oscillator for generating clock signals having different frequencies in response to the first control signal and the second control signal; and a pumping unit for generating the high voltage by performing a charge pumping operation in response to the clock signals.

Abstract: A low-power digital pulse-width modulator (DPWM) architecture for high frequency dc-dc switch-mode power supplies (SMPS) is disclosed that is well-suited for integration in power management systems of small handheld devices. The DPWM can operate in a stand-alone mode, without external clock, and can be implemented on a portion of silicon area needed for other DPWM solutions. In addition it has low power consumption and provides a good linearity of the input-to-output characteristic, also not characteristic for other architectures.

Abstract: A substrate bias voltage detection unit compares a level of a substrate bias voltage with a reference voltage in response to a self-refresh signal, an idle signal, and a refresh count signal so as to output an oscillating driving signal, enables the oscillating driving signal when the substrate bias voltage is equal to or higher than a first level in a normal mode, disables the oscillating driving signal when the substrate bias voltage is at a second level in a self-refresh mode, and disables the oscillating driving signal when the substrate bias voltage is at a third level in the self-refresh mode. An oscillation unit outputs an oscillating signal according to the oscillating driving signal. A voltage pumping unit controls pumping of the substrate bias voltage according to an output signal of the oscillation unit and then outputs a pumped substrate bias voltage.