Abstract: The phase controller device according to the invention comprises a hardware core that is formed by a signal detector, a voltage-controlled oscillator, a phase comparator, and an integration unit, where the hardware core, by controlling the working clock pulse frequency of the microcontroller, brings an output clock pulse signal that is generated by a microcontroller into phase with the input clock pulse information that is received from the input data stream, and does so in such a manner that the jitter is low. The microcontroller executes a program with this working clock pulse, where with that program the microcontroller generates the output clock pulse signal with an output clock pulse frequency that is in a predetermined division ratio to the control clock pulse frequency that is generated by the voltage-controlled oscillator and is given to the microcontroller as a working clock pulse frequency.

Abstract: A latch includes: an amplifying circuit, for receiving a first bias current in a first state for amplifying an input signal to generate an amplified signal; a latching unit, for latching the amplified signal and receiving a second bias current in a second state to output the amplified signal; and a biasing circuit, for providing a biasing current to the amplifying circuit, and providing the second biasing current to the latching unit. The biasing circuit includes: a first biasing module for providing a third biasing circuit to the amplifying circuit in the first state; and a second biasing module, for providing a fourth biasing current to the amplified circuit; wherein the first biasing circuit is equal to a sum of the third biasing current and the fourth biasing current.

Abstract: Provided is an analog/digital control delay locked loop (DLL). The DLL includes a phase detector for detecting a phase difference between an input clock signal and a feedback signal to provide an up detection signal or a down detection signal, a charge pump for generating an adjusted output current based on the up or down signals, a loop filter for low pass-filtering the output current to produce an analog control voltage, a voltage controlled delay Line (VCDL) for receiving the analog control voltage, the input clock signal and a digital code, and delaying the input clock signal based on the analog control voltage and the digital code to provide an output clock signal, a delay replica modeling unit formed by replica of delay factors for producing the feedback signal depending on the output clock signal, and a digital code generator for generating the digital code.

Abstract: An initialization signal generating circuit includes a voltage distributor, a first initialization signal generator, a second initialization signal, and a controller. The voltage distributor outputs a voltage signal in response to an external voltage. The first initialization signal generator outputs a first initialization signal in response to the voltage signal output from the voltage distributor. The second initialization signal generator outputs a second initialization signal in response to the voltage signal output from the voltage distributor. The controller blocks the external voltage supplied to the voltage distributor and the first and second initialization signal generators, in response to the first and second initialization signals.

Abstract: A semiconductor chip may include an internal circuit, at least one power gating transistor, a system manager, and/or at least one current regulator. The at least one power gating transistor may be configured to switch a supply of at least one drive voltage into the internal circuit. The system manager may be configured to generate a control signal corresponding to an activation state of the internal circuit. At least one current regulator may be configured to control an amount of a current flowing through the at least one power gating transistor in response to the control signal.

Abstract: A programmable gain amplifier comprises a current source that generates a first current based on a first transfer function. A voltage amplifier receives an input voltage signal and generates an output voltage signal based on a gain A, wherein the gain A is based on a control current and a second transfer function. A compensation module generates the control current based on the first current and a mapping function, wherein the mapping function is based on the first transfer function and the second transfer function to reduce the effect of an independent variable on an overall transfer function that relates the first current to the gain A.

Abstract: A compensated control circuit includes a combination module that generates a control variable based on n signals and a process module that generates an output signal based on an input signal and the control variable wherein n is a positive integer.

Abstract: A method and radiation hardened phase frequency detector (PFD) are provided for implementing enhanced radiation immunity performance. The radiation hardened phase frequency detector (PFD) includes a plurality of functional blocks. Each functional block includes duplicated components providing duplicated inputs, internal nodes and outputs. The duplicated components are arranged so that when there is a SEU hit to one node and the duplicated node supports the functionalities of the PFD.

Abstract: A method to detect a missing a clock pulse is provided. The method begins by providing a clock signal and a delayed clock signal. The delayed clock signal is then sampled to generate a sample of the delayed clock signal. A missing clock pulse may be detected if the sample of the delayed clock signal does not equal an expected value of the delayed clock signal.

Abstract: The impulse generator comprises a nonlinear transmission line capable of obtaining an impulse with a small half value width and a large amplitude, in which a plurality of transmission line units having a unit line unit and a diode are connected in series, a pulse generator connected to the transmission terminal of the nonlinear transmission line, and a bias-dependent element connected to the reception terminal of the nonlinear line, wherein the anode of the diode of the transmission line unit is connected to the transmission line and the cathode is connected to the ground, and one end of the bias-dependent element is connected to the reception terminal of the transmission line and the other end is biased to a negative potential.

Abstract: A power-on-reset (POR) circuit having a zero or substantially zero current state while the supply voltage is in a predetermined, valid range is disclosed. The POR circuit includes a state machine, an oscillator, and output circuitry that are electrically coupled to one another and to a supply voltage. Output from the output circuitry is also provided to the integrated circuit to which the POR circuit is coupled. The state machine includes a plurality of sequential circuits such as latches, flip-flops, and the like that are electrically coupled in a cascade, to provide a ripple counter. The output circuitry is structured and arranged to reset or initialize all of the logic elements on the chip by generating a POR output logic HI (1) signal by Boolean operation of the logic circuitry signal of the state machine for all Boolean states except one. The oscillator is disabled when the POR output logic signal is LO (0), which causes the POR circuit to enter a zero or substantially zero current state.

Abstract: A delay time adjusting method adjusts a delay time of an input signal so that a phase of the input signal and a phase of an output signal match each other. The delay time adjusting method comprises the step of delaying the phase of the output signal until a phase difference between the phase of the input signal and the phase of the output signal becomes N periods, where N is an integer other than zero.

Abstract: Systems and methods are disclosed herein to provide improved clock, delay, and skew techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a clock generator to provide a bias signal and a clock signal, with control logic providing a delay control signal based on the bias signal and a multi-bit control signal. A clock skew circuit provides a delay to the clock signal based on the delay control signal provided by the control signal. Memory coupled to the control logic provides the multi-bit control signal.

Abstract: A semiconductor device comprises a driver provided for a semiconductor element having a control electrode to which a drive voltage is applied, the semiconductor element being switched between the conduction state and the non-conduction state based on the drive voltage, the driver operative to apply the drive voltage to the control electrode; a detector operative to supply a voltage detection signal oscillating at a certain frequency to the control electrode to detect a first voltage having a certain relation to a voltage applied to the semiconductor element; and a controller operative to control the detector based on the first voltage detected at the detector.

Abstract: A system for controlling a slew rate of a signal, such as used in an imaging device, comprises a counter for measuring a duration that the signal drops from a maximum voltage to a predetermined reference voltage; a register for retaining a desired duration that the signal drops from the maximum voltage to the predetermined reference voltage; and a comparator for comparing the measured duration to the desired duration, the comparator being operative of a current source for the signal. An anti-oscillation circuit prevents the system from oscillating between two discrete durations.

Abstract: A phase discriminator for being used in a phase-locked loop to determine if a phase difference between a reference signal and a target signal has reached a programmable gap value is disclose which comprises a programmable phase gap selector receiving the reference signal, a first phase digital converter converting an output signal from the programmable phase gap selector to a first digital code, a second phase digital converter converting a phase difference between the target signal and the reference signal to a second digital code, and a code comparator comparing the first and second digital code and generating a first instructional signal based on a change of order of the values of the first and second digital code.

Abstract: In the case of a measuring device having a sensor supplied from an oscillator for a non-electrical variable and having a circuit arrangement downstream of the sensor for rectifying the output voltage of the sensor, interference pulses, which are superimposed on the output voltage of the movement sensor and are rectified when the output voltage of the movement sensor is rectified, falsify the measurement result. This is particularly true for spiked interference pulses having a high amplitude. In order to reduce such falsifications of the measurement result, the output voltage of the sensor is supplied to a ramp-generating circuit arrangement, in which the mathematical sign of the transmission behavior can be controlled. The mathematical sign of the transmission behavior of the ramp-generating circuit arrangement is controlled by a switching signal, whose flanks correspond to the zero crossings of the output voltage of the sensor.

Abstract: A spread spectrum clock generator includes: a phase frequency detector, for generating a phase difference signal according to a frequency divided signal and a reference signal with a reference frequency; a charge pump, for receiving the phase difference signal and generating an output current according to the phase difference signal; a loop filter, for receiving the output current and converting the output current to a voltage-controlled signal; a voltage-controlled oscillator, for receiving the voltage-controlled signal and generating a plurality of voltage-controlled output signals, wherein the plurality of voltage-controlled signals have a specific phase difference and a same voltage-controlled frequency; a frequency dividing unit, for receiving the plurality of voltage-controlled output signal and generating the frequency divided signal; and a delta-sigma modulator, for controlling the frequency dividing unit to have an equivalent divided value of (N+b)S+(N?a)(P?S) through receiving the frequency divided

Abstract: A high-side current sense circuit comprises a sense resistance Rsense connected in series with a signal having an associated current to be measured I, which develops voltages V1 and V2 on either side of Rsense. A differential gain stage powered by supply voltages VCC and VEE produces an output voltage which varies with the difference between its input signals. To keep the common mode portion of the input signal between voltages VCC and VEE, a voltage modification circuit subtracts or adds a common mode voltage to or from V1 and V2 to produce modified voltages V1? and V2?, which are coupled to the gain stage inputs. The voltage modification circuit is arranged to ensure that VEE?V1? and V2??VCC.

Abstract: A delay locked loop is disclosed which includes a clock selector for selecting and outputting any one of normal-phase and reverse-phase external clocks in response to a clock selection information signal, a first delay line for delaying an output signal from the clock selector by a predetermined amount of time, a second delay line for delaying an inverted version of an output signal from the first delay line by a predetermined amount of time, and a phase mixer for mixing a phase of the output signal from the first delay line and a phase of an output signal from the second delay line and outputting an internal clock having a corrected duty cycle as a result of the mixing.