Abstract: A supply switch circuit is provided for implementing a switchable on-chip high voltage supply. A stack of transistors is coupled between an on-chip high voltage supply and a circuit node. A control signal is coupled to the stack of transistors for selectively switching the high voltage supply to the circuit node. The control signal is coupled to a voltage divider included with the stack of transistors to limit a maximum node voltage within the stack of transistors.

Abstract: In order to improve a circuit arrangement (100) and a method of controlling at least one transistor (10, 12, 14, 18), especially of controlling the resistance value of at least one MOS transistor with vanishing DC modulation in such a way that a compensation of resistance variations without control deviation is also possible for the case where the transistor (10, 12, 14, 18) is operated with a vanishing DC voltage, i.e.

Abstract: An output stage interface circuit (1) comprises a main bipolar transistor (Q1) coupling a data output terminal (5) to a first rail (2) to which the positive of the power supply voltage (VDD) is applied, and a substrate diffusion isolated main NMOS transistor (MN1) coupling the data output terminal (5) to a second rail (3) which is held at ground. Control signals from a data control circuit (6) selectively operate the main bipolar transistor (Q1) and the main MOS transistor (MN1) for determining the logic high and low states of the data output terminal (5) during data output.

Abstract: A circuit for compensating for an offset voltage in a PhotoDetector Integrated Circuit (PDIC). The circuit includes a temperature detection unit, a current transfer unit and a current adjustment unit. The temperature detection unit generates a current that varies with variation in surrounding temperature. The current transfer unit transfers the generated current. The current adjustment unit adjusts the current transferred from the current transfer unit at a predetermined ratio and outputs the adjusted current.

Abstract: A CV conversion circuit capable of measuring a plurality of capacitances with a simple circuit is provided. A time-division signal is applied to each capacitor, whereby a plurality of capacitances of the capacitors can be measured in series by a circuit with a small number of components.

Abstract: A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal and an inverted clock signal and to obtain a delay signal that indicates a time difference between transitions of the clock signal and the inverted clock signal. The second circuit is configured to receive the clock signal and the inverted clock signal and the delay signal and to delay the clock signal based on the delay signal to provide an output clock signal having substantially a 50% duty cycle.

Abstract: A clocked scan flip-flop 2 is provided in which a latch 14 within the diagnostic data path is reused to store an operational signal value during a sleep mode. The operational signal value is supplied to the latch 14 via a sleep mode path 20 through a transmission gate 22 (or other tristate driver) controlled by a sleep mode control signal SLP. The diagnostic clock signal SCLK, the operational clock signal CLK and the sleep mode control signal SLP together provide the control operations for controlling the various elements within the clocked-scan flip-flop 2 to move into and out of sleep mode.

Abstract: A phase locked loop comprising a phase detector (100) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector (100) comprising: means (10) for obtaining a first one of said frequency control signals (U, D) by binary multiplication of the reference signal (Ref) and one of the relative phase shifted signals (I, Q); and means (20) for obtaining a second one of said frequency control signals (U, D) by binary multiplication of the relative phase shifted signals (I, Q).

Abstract: A multi-channel current regulator includes two or more channels, each channel acting as a current source or sink for a respective load. Each channel regulates its load current so that the load current is proportional to an input voltage supplied to the channel. An operational amplifier is shared between the channels. Each channel is selected in a rotating sequence for connection to the amplifier. As each channel is selected, a two-phase refresh cycle is initiated. During the first phase, the output of the amplifier is charged until it substantially matches the drive voltage of the selected channel. This is followed by the second phase where the output of the amplifier is adjusted until the load current of the selected channel is proportional to a set voltage Vset.

Abstract: A differential comparator with reduced offset. The differential comparator includes a first transistor coupled to a first input current and a second transistor coupled to a second input current. The first and second transistors are biased as diodes during a reset phase to store an offset voltage on parasitic capacitances of the first and second transistors. The first and second transistors are connected together as a latch to provide an output during a latch phase. Drain currents of the first and the second transistors substantially equal the first and the second input currents, respectively, during the reset phase and at the beginning of the latch phase. During the latch phase, currents approximately twice as large as differential-mode signal currents provided by the first and the second input currents are provided to the first and the second transistors, respectively.

Abstract: A high speed voltage level translator having minimum power dissipation and reduced area, specifically in the sub 0.1 micron domain, includes a transistorized arrangement to receive a low voltage input signal and to control current in the translated high level voltage signal. The translator further provides a differential amplifier arrangement for receiving the low level voltage input signal and provides feedback signals to the transistorized arrangement thereby outputting a high level voltage translated signal.

Abstract: Delay-locked loop integrated circuits include a duty cycle correction circuit. This duty cycle correction circuit generates at least one output clock signal having a substantially uniform duty cycle in response to at least one input clock signal having a non-uniform duty cycle. The duty cycle correction circuit is also responsive to a standby control signal that synchronizes timing of power-saving duty cycle update operations within the duty cycle correction circuit. These update operations reset the set point of the correction circuit.

Abstract: The invention system adjusts a phase/frequency detecting device in a phase locked loop. The phase/frequency detecting device compares a target clock signal generated from the phase locked loop with a predetermined reference clock signal, and outputs a set of control signals to further control the target clock signal to synchronize with the reference clock signal. A reset module counts the set of control signals and outputs a set of reset signals when a predetermined reset condition is met. A switch module counts the set of reset signals and switches the phase/frequency detecting device between a normal mode and a glitch protection mode when a predetermined switch condition is met. When the phase/frequency detecting device is under the glitch protection mode, and the predetermined reset condition set by the reset module is met, the reset module outputs the set of reset signals and resets the phase/frequency detecting device.

Abstract: In a duty adjustment circuit, a clock signal is frequency-divided to ½n by a frequency divider. In a first frequency doubler among n cascade-connected frequency doublers, the divided clock signal is delayed by a variable delay portion according to a control signal. The exclusive logical sum of the delayed signal and the divided clock signal in the frequency-doubling portion doubles the frequency. The average voltage of the frequency-doubled signal is detected by an average value detection portion, and is compared with a reference voltage by a comparison control portion. A control signal is fed back to the variable delay portion to cause the average voltage to become equal to the reference voltage. In this manner, a clock signal is generated from the last frequency doubler with frequency equal to that of the original clock signal, and with duty ratio adjusted to a desired value.

Abstract: A duty cycle detector comprising a first circuit configured to receive clock cycles including a first level and a second level. The first circuit is configured to obtain a first value based on the length of the first level and to obtain second and third values based on the length of the second level. The first value is compared to the second and the third values to determine a duty cycle range of the clock cycles.