Abstract: A method and apparatus are disclosed for generating multiple separate analog signals using a single microcontroller output pin. The microcontroller generates a waveform that is used to concurrently generate multiple separate analog signals. The microcontroller outputs a waveform that includes a first signal from one of the microcontroller's output pins. The first signal is used to produce a first analog signal. The microcontroller then outputs a delineating signal, as part of the waveform, from the microcontroller's output pin. The delineating signal indicates the start of a next signal in the waveform. The microcontroller then outputs a second signal, as part of the waveform, from its output pin. The second signal is used to produce a second analog signal. The waveform includes the first signal that is followed by the delineating signal that is followed by the second signal.

Abstract: The invention relates to a phase-locked loop circuit (1) in a radio transceiver for the detection of the linear operation of a first voltage controlled oscillator (2), which comprises a frequency divider (8), a reference oscillator (10), a phase detector (12) to compare the phases of the reference oscillator (10) with a divided frequency of the frequency divider (8), and a charge pumping means (14) connected to the phase detector (12) and is characterized in that the connection (13) between the phase detector (12) and the charge pumping means (14) has at least one branch-off line (15) connected to at least one filtering means (22), whose output voltage is related to the linear operation of the voltage controlled oscillator (2).

Abstract: An integrated circuit comprises an input for receiving a supply voltage, a field-effect transistor with a gate which is connected to the input in such a manner that the gate voltage present at the gate is a function of the supply voltage, a voltage source for generating a reference voltage which is connected to the input for receiving the supply voltage, a device for determining whether the gate voltage of the field effect transistor exceeds a turn-on voltage of the field-effect transistor, and a device for generating a ready signal which indicates that the supply voltage is high enough for performing functions of the integrated circuit, the device for generating being constructed for generating the ready signal when the gate voltage of the field-effect transistor exceeds the turn-on voltage of the field-effect transistor.

Abstract: Systems and methods are disclosed herein to provide improved clock, delay, and skew techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a clock generator to provide a bias signal and a clock signal, with control logic providing a delay control signal based on the bias signal and the control signal. A delay circuit provides a delay to the clock signal based on the delay control signal.

Abstract: A semiconductor integrated circuit device includes a comparator for making a comparison between a logical value of an input signal and a logical value of an output signal and outputting a combination signal having a combination of the logical values; and a flip-flop circuit configured to maintain a state of the output signal with electric power for maintaining the state less than electric power for state transition of the output signal in the case where the combination of the logical values of the combination signal is a predetermined combination, and wherein the comparator outputs the combination signal having the predetermined combination to an input terminal portion in the case of determining that the input signal does not vary the state of the output signal based on a result of the comparison between the logical value of the input signal and the logical value of the output signal.

Abstract: A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit.

Abstract: The invention relates to a circuit arrangement having connecting terminals (K1, K2) for application of a supply voltage (V+) and having a load transistor (M) for connecting a load (Z) to the supply voltage, said load transistor having a control terminal (G) and a first and second load terminal (D, S), the control terminal (G) of the load transistor (2) being coupled to a drive terminal (IN) for application of a drive signal (Sin). A voltage limiting circuit (10) is connected between one (D) of the load terminals and the drive terminal (G) of the transistor, a deactivation circuit (20) being provided, which is designed to deactivate the voltage limiting circuit (10) in a manner dependent on the supply voltage (V+).

Abstract: A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.

Abstract: A voltage-controlled current source and a frequency scanner using the same are provided. The voltage-controlled current source includes an impedance circuit, an amplifier, a transistor, and a current mirror. A first terminal of the impedance circuit is coupled to a common voltage. A first terminal of the amplifier is coupled to a second terminal of the impedance circuit, and a second terminal of the amplifier receives a control voltage. A gate of the transistor is coupled to an output terminal of the amplifier, and a first source/drain of the transistor is coupled to the other terminal of the impedance circuit. The current mirror is coupled to a second drain/source of the transistor, and includes a current output terminal, wherein a current output by the current output terminal is proportional to the current flowing through the transistor.

Abstract: In accordance with an embodiment of the present invention, a comparator system includes a plurality of multiplexers adapted to multiplex a number of differential input signals and a number of differential reference signals. A differencing circuit receives a differential input signal and a differential reference signal from the multiplexers and provides a differential output signal, which is used to provide a differential comparator output signal. A latch may be provided to perform differential-to-single ended conversion on the differential comparator output signal to provide a latch output signal. An output circuit may provide a registered digital output signal based on the latch output signal.

Abstract: A low power consumption in a semiconductor integrated circuit device can be achieved by reducing a glitch power in a flip-flop. In a pulse-generator-incorporated auto-clock-gating flip-flop in which data latch is performed by using a pulsed clock, input data is latched based on an output of a dynamic XOR circuit, which is a comparator circuit, during a period when the pulsed clock is at a high level, and the dynamic XOR circuit is cut off during a period when the pulsed clock is at a low level.

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit.

Abstract: A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit.

Abstract: A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.

Abstract: Methods, systems and components for use with or as a phase frequency detector. The phase frequency detector stretches its output pulse, allowing the detector to operate in a more linear region. As part of the invention, a new configuration for a D type flip flop is also disclosed. In one embodiment, the D type flip flop triggers at both the rising and the falling edges of the reference input, allowing a lower frequency input to be used while having the advantages of a higher frequency.

Abstract: A latch has a first mode in which the latch functions as a dynamic latch and a second mode in which the latch functions as a static latch. The latch has a feedback circuit that in turn has two parallel switchable loads. The first load is responsive to a data input signal of the latch in the first mode and disabled in the second mode. The second load is responsive to a clock signal in the second mode and disabled in the first mode. The switchable loads being in parallel provides for the ability to select the feedback that is better for the particular mode of operation. The first and second switchable loads can be optimized for the particular mode of operation that will use it.

Abstract: In a two-stage inverter circuit including an inverter circuit constituted by first and second FETs and an inverter circuit constituted by two FETs, a source and a gate of a third FET are connected to a first power source and a second power source, respectively. A drain of the third FET is connected to a source of the first FET. A source and a gate of a fourth FET are connected to the first power source and the second power source, respectively. A drain of the fourth FET is connected to a source of a seventh FET. A gate of the seventh FET is connected to the second power source, and a drain of the seventh FET is connected to a back gates of the first, third, fourth, seventh and fifth FETs. The drain of the third FET is connected to the drain of the fourth FET.

Abstract: An integrated circuit compensates for power supply voltage dependent delay using a clock circuit that is responsive to a power supply voltage measuring circuit. The clock circuit modifies a phase relationship based on a measured power supply voltage value.

Abstract: Methods and apparatus are provided for delay line control using receive data. A delay in a Delay-Locked-Loop circuit is controlled by obtaining a plurality of samples of one or more received signals for each unit interval; determining a data eye width in the one or more received signals; and adjusting a delay of at least one clock signal based on the data eye width. For example, the measured data eye width can be compared to a predefined value, such as a desired or ideal value. Generally, the delay is not adjusted in accordance with the present invention until the Delay-Locked-Loop circuit has reached a locked condition based on one or more predefined criteria.