Abstract: A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked ioop generating one or more delayed periodic signals and a control signal for controlling the time delay between the periodic input signal and the delayed periodic signals. The delay circuit also includes a controlled delay circuit for generating one or more delayed periodic signals. The controlled delay circuit has an input terminal for receiving at least one of the delayed periodic signals from the delay locked loop and a delay control terminal coupled to the control signal from the delay locked ioop for controlling the time delay between the delayed periodic input signal received from the delay locked loop and the one or more delayed periodic signals generated by the controlled delay circuit.

Abstract: A high voltage-generating circuit comprises a control circuit for generating a control signal for executing an operation command and generating a refresh signal depending upon a refresh operation, an oscillator driven according to an enable signal, for outputting an oscillation signal the cycle of which is controlled according to a refresh signal, a charge pump circuit for generating a high voltage using a power source voltage according to the oscillation signal, wherein the charge pump circuit has the ascent rate of the high voltage controlled according to variation in the cycle of the oscillation signal, and a level detection circuit for comparing the high voltage and a reference voltage to determine whether the high voltage reaches a target value, and controlling the operation of the oscillator according to the result of the comparison.

Abstract: A comparator has first and second current paths, each passing from an input through a transistor, through a current source to ground, the second current path also having a reference voltage drop element coupled in series with the second input. The gates of the transistors are coupled to form a current mirror. The reference voltage drop element enables higher voltages to be input and compared to higher thresholds above an internal supply voltage level without the need for dividing resistors to reduce the input voltage. Avoiding such resistors means the power dissipation and the silicon area used can be kept lower. ESD vulnerability is reduced since the inputs are not coupled to gates of MOS transistors. Overvoltage protection across the source and gate of the second transistor can be added.

Abstract: A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first transistor also is coupled to a voltage source. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports, a slave feedback loop and a second transistor coupled to the slave feedback loop. The second transistor is coupled to the voltage source or a different voltage source. When a clock signal is in a first state, the first single transistor is activated to reset the digital storage element. When the clock signal is in a second state, the second single transistor is activated to reset the digital storage element.

Abstract: A step-down voltage output circuit preventing: latch-up phenomenon in a load circuit for a period between a power-supply activation and complete start of a charge pump circuit; and rapid change of a substrate potential when a step-down voltage output is changed from ON to OFF. The step-down voltage output circuit has a timer circuit that operates depending on control signals and a timer period; a first N-channel MOS transistor in which a source is connected to a step-down voltage output terminal, a drain is connected to ground, a gate is connected to a power-supply voltage input terminal through a resistance; and a second N-channel MOS transistor in which a source is connected to the step-down voltage output terminal, a drain is connected to the gate of the first N-channel MOS transistor, and a gate is connected to an output terminal of the timer circuit.

Abstract: Provided is a temperature-compensated circuit for a power amplifier through diode voltage control, in which a first resistor (Rref), a first diode (D1), and a second diode (D2) are connected to a reference voltage in series. The temperature-compensated circuit includes a second resistor (R1) connected to the reference voltage, a third resistor (R2) connected to the second resistor in series, a fourth resistor (Rc) having one terminal connected to the reference voltage, a fifth resistor (Re) having one terminal connected to ground, a bias transistor having a base terminal connected to a contact point (VS) between the second resistor and the third resistor, a collector terminal connected to the other terminal of the fourth resistor, and an emitter terminal connected to the other terminal of the fifth resistor, and a sixth resistor (Rf) connected between a series connection terminal between the first diode and the second diode, and the collector terminal of the bias transistor.

Abstract: A duty cycle corrector, including a first, second circuit and a third circuit is disclosed. The third circuit is configured to obtain a threshold value in response to charge flow that is regulated by the first circuit and the second circuit, wherein the first circuit is configured to receive a clock signal and change the charge flow at a first transition of the clock signal. The second circuit is configured to change the charge flow at a second transition of the clock signal. The first circuit and the second circuit are configured to change the charge flow in response to obtaining the threshold value.

Abstract: An n-stage charge pump contains n primary capacitive elements (CC1-CCn or CD1-CDn), n+1 charge-transfer cells (601-60n+1, 1101-110n+1, 1201-120n+1, or 1301-130n+1) respectively sequentially designated as the first through (n+1)th cells, and sources of first and second clock signals (VCKP and VCK P or VCKP1 and VCKP2) approximately inverse to each other. Each pump stage (62i, 112i, 122i, or 132i) includes one (CCi or CDi) of the capacitive elements and a corresponding one (60i, 110i, 120i, or 130i) of the first through nth charge-transfer cells. Each cell contains a charge-transfer FET (PTi or NTi). A pair of side FETs (PSi and PDi or NSi and NDi) are provided in the first cell, in the (n+1)th cell, and normally in each remaining cell. The side FETs in the first cell or/and the (n+1) cell are connected in such a manner as to avoid undesired bipolar action that could cause degradation in the pump's voltage gain.

Abstract: The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the other electrode of the capacitor, an accurate operation can be obtained without being influenced by variations in the TFT characteristics even when the amplitude of an input signal is small relatively to the width of a power supply voltage.

Abstract: A level shift circuit having a latch function includes a precharging PMOS transistor MP1 which is turned on in a precharge period to interrupt a through current of an input stage, an NMOS transistor MN1 which inputs data and performs discharging in a data input period, and a transistor MP2 for holding data after level shifting. Thus, each of the transistors can have a minimum configuration. Since the level shift circuit has a latch function, it is possible to omit a circuit for latching input data, thereby reducing a circuit area.

Abstract: Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.

Abstract: Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are selectively coupled through a variable delay line to synchronize two clock signals.

Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer that receives the functional data signals and selectively outputs one of the functional data signals. The element comprises a slave transparent latch coupled to the master transparent latch and comprising dedicated functional and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping. A first transistor is coupled to the master transparent latch and a second transistor is coupled to the slave transparent latch. When activated, the first or second transistor resets the element.

Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.

Abstract: The smart charge-pump circuits basically include a high-performance charge-pump circuit as well as a smart lock-in circuit. After the smart charge-pump circuit sensors an initial condition and responds accordingly, it will begin to operate fully as a high performance charge-pump.

Abstract: A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of transistors. A pair of resistive elements is connected between the first pair and second pair of transistors so as to increase bias currents shared by the first and second pairs of transistors. The increased bias currents reduce a time required by the differential comparator to transition from a meta-stable state to a stable state, thereby improving a bit-error rate of the differential comparator. The resistive elements can use linear resistors or transmission gates. Gates of either the first or second pair of transistors can provide an output.

Abstract: A combined output driver for TMDS signals and LVDS signals. First and second output drivers output first and second differential signals to a first external input unit and a second external input unit, respectively, through a pair of signal lines according to first and second input signals. In the second output driver, a driver buffer is coupled to a first voltage and a first node respectively to generate two control signals according to the second input signals. An output unit generates the second differential signal according to the two control signals. A power supply provides a second voltage higher than the first voltage to power the driver buffer and the output unit when the first output driver outputs the first differential signal to the first external input unit.

Abstract: A combined output driver for TMDS signals and LVDS signals. A first output driver includes a first differential unit generating a first differential according to first input signals in a first mode and a first clamping device coupled between the first node and the first differential unit to clamp potentials at two power terminals below a second power voltage. The second output driver includes a second differential unit generating a second differential signal according to second input signals in a second mode and a second clamping device to clamp potentials at two output terminals of the second differential unit below the second power voltage.

Abstract: A semiconductor device that includes a clock generator which generates a clock signal; a booster which boosts a supply voltage by using the clock signal to output the boosted voltage; a potential detector which detects an output potential of the booster to output a frequency changing signal depending on the output potential; and a frequency changer which is interposed between the clock generator and the booster to change the frequency of the clock signal from the clock generator to the booster on the basis of the frequency changing signal.

Abstract: A differential bus network, in general, or a controller area network (CAN) driver, in particular, controls and minimizes the variation on the common-mode signal of the CAN bus. This CAN driver also provides improved symmetry between its differential output signals, CANH and CANL, and provides protection for its low voltage devices from voltage transients occurring on its output lines. The common-mode signal is sensed and buffered, then during the dominant to recessive transition, the bus signals are shorted to the buffered common mode voltage. Specifically, additional switches or transistors are used to pull the differential output signals, CANH and CANL, to the common mode signal VCM when the state of the CAN bus transitions from dominant to recessive. This improvement minimizes high frequency spikes in the common-mode signal and eliminates DC shifts during transitions of the state of the CAN bus.