Abstract: A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

Abstract: The present application relates to the field of servers, and discloses a cross-cabinet server memory pooling method, apparatus and device, a server, and a medium, used for pooling server memories. Considering that the memory use conditions of different server cabinets in the same server cluster are different, a communication device is built between different server cabinets in the present application; a server cabinet may apply another server cabinet for the memory use permission of a first target device; after the memory use permission is successfully applied, a device memory may be used across the cabinets, so that the memory use requirements of server cabinets are met while the number of memory devices is not increased, and the resource utilization rate is improved.

Abstract: A data processing device includes a data capturing module, a first counting module, a data moving module and a data recovery module. The data capturing module generates and temporarily stores N pieces of data according to an input signal and a first counting value, and generates a data moving instruction according to a second counting value and a first predetermined value. The first counting module generates the second counting value according to the N pieces of data. The data moving module moves the N pieces of data according to the data moving instruction. The data recovery module performs a recovery processing on the N pieces of data according to the second counting value to generate N pieces of recovery data.

Abstract: Technologies for storing streaming data include, in some embodiments, in response to determining that the chunk size satisfies a chunk size threshold and the streaming data is sequential data of a size that satisfies a threshold sequential data size, writing the sequential data to a first file system partition of a file system comprising a plurality of file system partitions, and in response to determining that the chunk size does not satisfy the chunk size threshold or the chunk size satisfies the chunk size threshold and the streaming data is the first type of metadata, writing the streaming data to a second file system partition of the plurality of file system partitions.

Abstract: A data storage device includes a memory controller and a media controller. The memory controller is configured to provide a request signal related to an operation of a memory device. The media controller is configured to receive the request signal from the memory controller and provide a command to the memory device.

Abstract: Techniques for application mobility in an information processing system environment are disclosed. For example, a method comprises managing, via an automatic data mover selection controller, a plurality of data movers to select at least one of the plurality of data movers for use in moving data associated with an application program from a first storage location to a second storage location.

Abstract: A storage device includes a storage array with multiple planes organized as plane groups, where the planes of a plane group receive and process commands in parallel. The storage device includes a storage controller that receives a command from a host controller. In response to receipt of the command the storage controller provides ready information for all planes to the host controller. The multiple planes can optionally have independent multiplane read operation (IMPRO). Each plane group can have a first plane and a second plane, and the storage controller can optionally read data from the first plane of a plane group in response to a virtual ready signal for the first plane, before the second plane of the plane group is ready.

Abstract: The disclosed technology may comprise a mechanism that provides address range based memory hints, based on software memory access patterns. The mechanism includes an interface that can be in the form of a new instruction (“mem_range_hint”) that includes as operands (i) the start of the virtual address (“start_vaddr”), (ii) memory region size (“size”), and (iii) a hint (“hint”) associated with the memory access pattern.

Abstract: The disclosure includes a system and methods provide for optimizing performance of disaggregated memory architectures in terms of time and energy. Examples of the systems and methods disclosed herein provide for a near memory compute proximate to a disaggregated memory that can be implemented to receive, from a compute node, one or more requests to perform computation functions on data stored at the disaggregated memory and collect telemetry data for the disaggregated memory, a near memory compute proximate to the disaggregated memory, and the compute node. The systems and methods disclosed herein can also model a plurality of configurations for executing the one or more requests based on the telemetry data, select a modeled configuration of the plurality of modeled configurations for executing the one or more requests, and assign one or more of a plurality of data operators of the near memory compute according to the selected modeled configuration.

Abstract: A volume management server may regularly check the status of persistent volumes to determine if they have been released. A database with information about the persistent volumes may be updated to indicate a current date as the release date when a persistent volume is found to be released without a release date. This enables the volume management server to determine, in the future, how long the persistent volume has been released. When the difference between the current date and the release date for a persistent volume reaches a first predetermined age threshold, the volume management server notifies a set of users. When the difference between the current date and the release date for the persistent volume reaches a second predetermined age threshold, the volume management server causes deletion of the persistent volume.

Abstract: The present disclosure provides methods and apparatuses for programming operating system (OS) data before a surface mount technology (SMT) process. In some embodiments, a method includes erasing a plurality of memory cells in a memory block, classifying word lines coupled to the memory block into first word lines to be programmed with OS data and second word lines to be programmed in a state pattern, programming, with a multi-bit program, the OS data into first memory cells of the plurality of memory cells coupled to the first word lines, and programming second memory cells of the plurality of memory cells coupled to the second word lines to have the state pattern.

Abstract: Examples described herein relate to federated management of data operators across multiple near-memory compute (NMC) nodes attached to memory devices in a network-attached memory system. Federated management includes loading, executing, and scaling data operators across the multiple NMC nodes together as a group. Examples include receiving a data access request from a client application and loading data operators in the multiple NMC nodes based on a data access pattern associated with the data access request. Examples include scaling the data operators based on performance metrics for the data operators or the multiple NMC nodes in correlation with client application performance. The multiple NMC nodes may dynamically scale the data operators based on request-load, execution frequency of data operators, resource availability, or other scaling strategies. Examples also include loading and scaling the data operators based on one or more of request characteristics or data operator characteristics.

Abstract: A storage system, a file storage and reading method, and a terminal device are provided. A storage system including a UFS is used as an example. The storage system configures different medium forms of the UFS, for example, configures persistent storage space of the UFS including SLC and TLC medium forms, to implement hybrid medium multi-disk storage. Based on the storage system, a hot file related to an application running rate is preferentially selected and stored in an SLC storage area of the UFS, and files on a mapped multi-disk are mounted on a same directory of a file system, so that files can be migrated between the SLC storage area and a TLC storage area without user perception, to improve performance of the storage system.

Abstract: Disclosed is a storage device which includes a nonvolatile memory device, and a storage controller that controls the nonvolatile memory device and updates metadata based on an operation of the nonvolatile memory device, and the storage controller includes a journal data generator that generates a plurality of journal data associated with the update of the metadata, and a journal data replayer that replays the plurality of journal data in parallel to restore the metadata.

Abstract: A method for controlling a data allocatable neural processing unit is provided. The method may comprise: determining a dependency determination between data blocks of a specific layer of at least one neural network model; allocating memory banks to store the data blocks based on the dependency determination; and storing each data block in the allocated memory bank.

Abstract: A method, a system and an accelerator for managing memory access among one or more computing entities may continuously monitor data access to at least one memory module, associated with a respective source computing entity. Based on the monitoring, embodiments may identify a memory area of the source memory module that contains a predetermined quantity of data that is expected to be used by a sink computing entity, and transmit a first version of content of the identified memory area to the sink computing entity. Embodiments may then identify an explicit request, from the sink computing entity to the source computing entity, for accessing data of the identified memory area. Embodiments may subsequently calculate a difference between the first version of content of the identified memory area and a current content of the identified memory area, and transmit the calculated difference to the requesting sink computing entity.

Abstract: In an aspect, the disclosure is directed to a cell erase method which includes not limited to: initiating an erase operation of a block of memory cells by applying an erase condition to the block of memory cells; performing a first erase verification procedure for at least a portion of the block of memory cells in comparison with a first erase verify voltage; adjusting the first erase verify voltage in response the portion of the block of memory cells having passed the first erase verification procedure; performing a second erase verification procedure for the block of memory cells in comparison with the adjusted erase verify voltage; performing a post program verification procedure for the block of memory cells in comparison with a post program verify voltage to detect leakage current of the block of memory cells; determining whether the adjusted erase verify voltage reaches a final erase verify voltage.

Abstract: A memory system is connectable to a host having a host memory and includes a non-volatile memory that stores management data, a memory controller configured to manage caching of parts of the management data in cache lines of the host memory, and a first memory configured to store a bitmap that includes a bit indicating whether the memory controller has accessed first data stored in the host memory after power was last supplied to the memory system. The first data indicates whether or not a part of the management data corresponding thereto is stored in one of the cache lines, and the memory controller is configured to perform either a first operation of reading the first data from the host memory or a second operation of reading an initial value of the first data managed by the memory controller, based on the bitmap.

Abstract: The present disclosure discloses a virtual memory management method and apparatus supporting physical addresses larger than virtual addresses. The method comprises steps of: determining a target virtual address corresponding to an instruction fetch address or a load storage address in any one of a user mode, a supervisor mode, or a machine mode; determining a target physical address corresponding to the target virtual address by accessing a virtual memory management unit, the virtual memory management unit being internally provided with page table entries that map virtual addresses to physical addresses, the bit width of the target virtual address being possibly less than or equal to that of the target physical address, particularly in a many-core application field; and finally, returning the target physical address to a corresponding instruction fetch unit or load memory unit, thereby ensuring the correctness and validity.

Abstract: A first data entry is written to an address location of a memory resource that is neither a first physical address nor a last physical address. In response to a determination that a second data entry has a value that is greater than a value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the last physical address. In response to a determination that the second data entry has the value that is less than the value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the first physical address.