Abstract: In an aspect, the disclosure is directed to a cell erase method which includes not limited to: initiating an erase operation of a block of memory cells by applying an erase condition to the block of memory cells; performing a first erase verification procedure for at least a portion of the block of memory cells in comparison with a first erase verify voltage; adjusting the first erase verify voltage in response the portion of the block of memory cells having passed the first erase verification procedure; performing a second erase verification procedure for the block of memory cells in comparison with the adjusted erase verify voltage; performing a post program verification procedure for the block of memory cells in comparison with a post program verify voltage to detect leakage current of the block of memory cells; determining whether the adjusted erase verify voltage reaches a final erase verify voltage.

Abstract: A memory system is connectable to a host having a host memory and includes a non-volatile memory that stores management data, a memory controller configured to manage caching of parts of the management data in cache lines of the host memory, and a first memory configured to store a bitmap that includes a bit indicating whether the memory controller has accessed first data stored in the host memory after power was last supplied to the memory system. The first data indicates whether or not a part of the management data corresponding thereto is stored in one of the cache lines, and the memory controller is configured to perform either a first operation of reading the first data from the host memory or a second operation of reading an initial value of the first data managed by the memory controller, based on the bitmap.

Abstract: The present disclosure discloses a virtual memory management method and apparatus supporting physical addresses larger than virtual addresses. The method comprises steps of: determining a target virtual address corresponding to an instruction fetch address or a load storage address in any one of a user mode, a supervisor mode, or a machine mode; determining a target physical address corresponding to the target virtual address by accessing a virtual memory management unit, the virtual memory management unit being internally provided with page table entries that map virtual addresses to physical addresses, the bit width of the target virtual address being possibly less than or equal to that of the target physical address, particularly in a many-core application field; and finally, returning the target physical address to a corresponding instruction fetch unit or load memory unit, thereby ensuring the correctness and validity.

Abstract: A first data entry is written to an address location of a memory resource that is neither a first physical address nor a last physical address. In response to a determination that a second data entry has a value that is greater than a value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the last physical address. In response to a determination that the second data entry has the value that is less than the value associated with the first data entry, the second data entry is written to an address location that is physically located between the address location of the memory resource to which the first data entry is written and the first physical address.

Abstract: Systems and methods for implementing maintenance operations on storage devices in place of drive-based maintenance operations are disclosed. According to an aspect, a system includes a storage controller configured to receive a plurality of media scan configurations for maintenance from a plurality of storage devices. The data maintenance algorithms implemented across storage device and storage controller is also configured to tune and/or disable drive-based maintenance routines on one or more of the plurality of storage devices. Further, the BMC and/or storage controller is configured to perform controller-based maintenance operations in replacement of the drive-based maintenance routines of the one or more of the plurality of storage devices based on the received plurality of media scan configurations.

Abstract: One example method includes assigning, at a production site, a priority to a portion of a dataset to be backed up, checking to determine if the priority meets or exceeds a threshold priority; and, when the priority meets or exceeds the threshold priority, and when an air gap between the production site and a storage vault is closed, backing up, by way of the closed air gap, the portion of the dataset to the storage vault.

Abstract: A method of operating a storage device including a nonvolatile memory, the method including: generating virtual domains each of which including page mapping and block mapping tables; receiving a data input/output (I/O) request; performing a data I/O operation corresponding to the data I/O request using the virtual domains; transmitting a data I/O response to a host device in response to the data I/O request and the data I/O operation; and changing at least one of the virtual domains based on a direct request from the host device or a change in a first parameter associated with the data I/O request, and wherein, in response to the first parameter being changed, a second parameter associated with the data I/O response is changed by changing at least one of the virtual domains and by performing the data I/O operation using the changed virtual domain.

Abstract: In an embodiment, an apparatus includes a memory access controller to be coupled to a memory and a memory management unit (MMU) coupled to the memory access controller. The MMU is to receive a memory transaction comprising an original transaction security attribute from a first device; responsive to the memory transaction comprising a first physical address of the memory, transmit the memory transaction to the memory access controller; and responsive to the memory transaction comprising a virtual address, generate a translated memory transaction comprising a translated physical address of the memory based on the virtual address and a translated transaction security attribute and transmit the translated memory transaction to the memory access controller, the translated physical address and the translated transaction security attribute associated with an operating system (OS) memory region of the memory associated with an OS. Other embodiments are described and claimed.

Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may collect, by an association rule mining (ARM) model, file system data from a host file system, the file system data defining at least one attribute of a file. The controller may receive, from the host, a memory command associated with the file. The controller can associate, by the ARM model, the at least one attribute with the file. The controller may perform the memory command based on the association of the at least one attribute with the file.

Abstract: Methods, systems, and devices for suspend operations are described. A memory device may perform a write operation including one or more programming phases and one or more verify phases. The memory device may receive a read command while performing the write operation and determine whether the verify phase of the write operation is complete. The memory device may suspend a performance of the write operation in response to determining that the verify phase of the write operation is complete. The memory device may transmit first information for the write operation from a first latch to a volatile memory device in response to suspending the performance of the write operation. The memory device may perform a read operation associated with the read command in response to suspending the performance of the write operation and transferring the first information.

Abstract: This document describes techniques for storing virtual disk payload data. In an exemplary configuration, each virtual disk extent can be associated with state information that indicates whether the virtual disk extent is described by a virtual disk file. Under certain conditions the space used to describe a virtual disk extent can be reclaimed and state information can be used to determine how read and/or write operations directed to the virtual disk extent are handled. In addition to the foregoing, other techniques are described in the claims, figures, and detailed description of this document.

Abstract: A memory controller configured to control a dynamic random access memory (DRAM) includes a first control circuit and a second control circuit. The first control circuit is configured to store a request received by the memory controller in a first storage circuit, and select a request from all requests stored in the first storage circuit. The second control circuit is configured to store the request selected by the first control circuit in a second storage circuit, reorder requests stored in the second storage circuit, generate a DRAM command, and issue the DRAM command to the DRAM. The first control circuit is configured to select the request based on target banks and target pages of the requests stored in the second storage circuit, and a state of a bank or page of the DRAM.

Abstract: The present disclosure describes techniques for improving data processing. At least one transaction may be generated by a file system driver associated with a host. Each transaction comprises logical block addresses (LBAs) and information associated with at least one function. The at least one transaction may be journaled into a computational storage for offloading data processing from the host to the computational storage. The computational storage comprises a persistent memory and at least one field-programmable gate array (FPGA) core. The offloading of the data processing comprises offloading journal replay operations to the computational storage. The journal replay operations comprise applying the at least one function to at least one subset of the LBAs by the at least one FPGA core.

Abstract: A semiconductor device includes terminals connectable to a host, first and second bridge chips connected to the terminals, first chips connected to the first bridge chip, and second chips connected to the second bridge chip. The terminals includes a first terminal through which a first signal designating a bridge chip is transmitted. The first bridge chip is configured to enable signal transmission to at least one of the first chips when the first signal designates the first bridge chip, and disable the signal transmission to the first chips when the first signal does not designate the first bridge chip. The second bridge chip is configured to enable signal transmission to at least one of the second chips when the first signal designates the second bridge chip, and disable the signal transmission to the second chips when the first signal does not designate the second bridge chip.

Abstract: A request processing method and apparatus, a device, and a non-transitory readable storage medium. When modifying reflink data, in the present application, first reading continuous data including currently modified data from a disk to a cache, then modifying corresponding reflink data in the cache, but not modifying other data in the continuous data, and then allocating a new address for the modified new reflink data in the disk, and mapping the cache address of the new reflink data to the new address, so as to store the new reflink data in the new address, and at the same time reducing the reference count of the corresponding reflink data in the reflink shared tree by one. In this solution, there is only one read operation and one write operation for the disk, so the problem of write amplification is reduced.

Abstract: A method for memory allocation may include determining an amount of use for a first memory page, wherein the first memory page is mapped to a first page group of a first group level, a second memory page may be mapped to a second page group of the first group level, and the first memory page and the second memory page may be mapped to a third page group of a second group level, and selecting, based on an allocation request, the first memory page based on the amount of use. The amount of use may include a first amount of use, and the method may further include determining a second amount of use for the second memory page, wherein the first memory page may be selected based on the first amount of use and the second amount of use.

Abstract: A storage device including: a memory storing data based on program modes; and a storage controller including a program mode table, the storage controller configured to: in response to a program request and first data being already stored in the memory, perform a deduplication operation in which the first data is logically and not physically programmed, in response to the program or an erase request, update a count value from a first to a second value, and in response to a determination that a first program mode corresponding to the first value and a second program mode corresponding to the second value are different, transmit a first command and address to the memory such that a first program operation in which the first data programmed with first bits corresponding to the first program mode is re-programmed with second bits corresponding to the second program mode is performed.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may: determine a first value associated with vibrations within an information handling system (IHS); determine that the first value meets or exceeds a first threshold value; after determining that the first value meets or exceeds the first threshold value: receive first data to store via at least one hard disk drive; and store the first data via at least one solid state memory medium; determine a second value associated with vibrations within the IHS; determine that the second value does not meet or exceed the first threshold value; and in response to determining that the second value does not meet or exceed the first threshold value: retrieve the first data from the at least one solid state memory medium; and store the first data via the at least one hard disk drive.

Abstract: Devices and techniques for efficient obfuscated logical-to-physical mapping are described herein. For example, activity corresponding to obfuscated regions of an L2P map for a memory device can be tracked. A record of discontinuity between the obfuscated regions and L2P mappings resulting from the activity can be updated. The obfuscated regions can be ordered based on a level of discontinuity from the record of discontinuity. When an idle period is identified, an obfuscated region from the obfuscated regions is selected and refreshed based on the ordering.

Abstract: According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.