Abstract: A storage device including: a memory storing data based on program modes; and a storage controller including a program mode table, the storage controller configured to: in response to a program request and first data being already stored in the memory, perform a deduplication operation in which the first data is logically and not physically programmed, in response to the program or an erase request, update a count value from a first to a second value, and in response to a determination that a first program mode corresponding to the first value and a second program mode corresponding to the second value are different, transmit a first command and address to the memory such that a first program operation in which the first data programmed with first bits corresponding to the first program mode is re-programmed with second bits corresponding to the second program mode is performed.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may: determine a first value associated with vibrations within an information handling system (IHS); determine that the first value meets or exceeds a first threshold value; after determining that the first value meets or exceeds the first threshold value: receive first data to store via at least one hard disk drive; and store the first data via at least one solid state memory medium; determine a second value associated with vibrations within the IHS; determine that the second value does not meet or exceed the first threshold value; and in response to determining that the second value does not meet or exceed the first threshold value: retrieve the first data from the at least one solid state memory medium; and store the first data via the at least one hard disk drive.

Abstract: Devices and techniques for efficient obfuscated logical-to-physical mapping are described herein. For example, activity corresponding to obfuscated regions of an L2P map for a memory device can be tracked. A record of discontinuity between the obfuscated regions and L2P mappings resulting from the activity can be updated. The obfuscated regions can be ordered based on a level of discontinuity from the record of discontinuity. When an idle period is identified, an obfuscated region from the obfuscated regions is selected and refreshed based on the ordering.

Abstract: According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.

Abstract: Methods, systems, and devices for improved techniques for partial writes are described. A memory device may include a non-volatile memory and a volatile memory configured to operate as a cache for the non-volatile memory. The memory device may receive, from a host device, a write command for a first data set provided by the host device. Based on the write command, the memory device may store the first data set in a buffer coupled with a volatile memory. After storing the first data set in the buffer, the memory device may communicate to the volatile memory a set of data that includes the first data set and a second data set. The first data set and the second data may be associated with adjacent addresses for the volatile memory and may each have sizes smaller than a threshold size associated with the volatile memory.

Abstract: Systems and methods for providing and/or facilitating live browsing of granular mail or mailbox data, such as data stored within Exchange mailboxes, are described. For example, the systems and methods may provide mechanisms for browsing and/or restoring granular data (e.g., email data) from an Exchange database backup copy (or other secondary copy), without having to restore the entire database from the backup copy.

Abstract: Technologies for storing streaming data include, in some embodiments, in response to determining that the chunk size satisfies a chunk size threshold and the streaming data is sequential data of a size that satisfies a threshold sequential data size, writing the sequential data to a first file system partition of a file system comprising a plurality of file system partitions, and in response to determining that the chunk size does not satisfy the chunk size threshold or the chunk size satisfies the chunk size threshold and the streaming data is the first type of metadata, writing the streaming data to a second file system partition of the plurality of file system partitions.

Abstract: A method of data caching includes; determining a process corresponding to a read request communicated from a host, obtaining historical access information for the process according to historical process information stored in a cache, wherein the historical process information includes at least one of historical access information for the process and heat information for one or more regions historically accessed by the process, determining a first region historically accessed by the process according to the historical access information, such that heat information for the first region satisfies a first preset condition, and loading a physical address for the first region from a storage device to the cache.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to add one or more entries to a log file system (LFS) invalidation table and scan the LFS invalidation table during a storage optimization operation. Each entry of the one or more entries maps a new valid logical block address (LBA) to an old invalidated LBA. The new valid LBA is updated version of the old invalidated LBA. The storage optimization operation includes moving data from a first location to a second location.

Abstract: A computing system includes a volatile memory, a cache coupled with the volatile memory, and a processing device coupled with the cache and at least one of a storage device or a network port. The processing device is to: generate a plurality of virtual addresses that are sequentially numbered for data that is to be at least one of processed or transferred in response to an input/output (I/O) request; allocate, for the data, a continuous range of physical addresses of the volatile memory; generate a set of hash-based values based on mappings between the plurality of virtual addresses and respective physical addresses of the continuous range of physical addresses; identify a unique cache line of the cache that corresponds to each respective hashed-based value of the set of hash-based values; and cause the data to be directly stored in the unique cache lines of the cache.

Abstract: A memory adaptive temperature controlling method, a storage device, and a control circuit unit are provided. In this exemplary embodiment, the temperature value is obtained according to the temperature measured by the thermal sensor, and the access speed to be reached is calculated according to the temperature change rate within the specific time range and the adjustment percentage when it is determined that the speed-down or speed-up operation is required to be performed. By adjusting the access speed of the memory storage device in a stepwise manner, the temperature of the memory storage device may be stabilized, thereby striking the balance between the temperature stability and the system performance of the memory storage device.

Abstract: A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.

Abstract: A method of controlling a storage device including a command terminal, a plurality of data terminals, and a clock terminal, including receiving a clock signal through the clock terminal; outputting a first status data through the data terminals in accordance with only one of a rising edge and a falling edge of the clock signal in a first transfer mode; outputting data through the data terminals in accordance with both the rising edge and the falling edge of the clock signal in a second transfer mode; and receiving and responding to commands via the command terminal in accordance with only one of a rising edge and a falling edge of the clock signal while outputting data through the data terminals in accordance with both the rising edge and the falling edge of the clock signal in the second transfer mode.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device is DRAM-less. The controller is configured to determine that a connection to a host memory buffer (HMB) of a host device is lost, load a most recent copy of a flash translation layer (FTL) table from the memory device, generate one or more updates to the most recent copy of the FTL table, and re-enable command fetching. The controller is further configured to mark one or more commands in a command database with an error condition upon the determining. After a boot of the connection, the controller is further configured to copy the FTL tables from the memory device to the HMB, work on commands, save FTL table differences between the HMB and the memory device, and update the FTL tables in the memory device.

Abstract: An information processing apparatus including a memory and a memory controller writing data to the memory in response to a write for writing the data to the memory, in which the memory executes error correction processing for each data of a predetermined data length, and the memory controller executes, in place of the memory, read modify write processing in a case where a data length of the data related to the write instruction is smaller than the predetermined data length.

Abstract: A method includes writing a first codeword to a first set of contiguous partitions in a first memory die of a memory device. The method further includes writing a first portion of a second codeword to a second set of contiguous partitions in the first memory die of the memory device and writing a second portion of the second codeword to a first set of contiguous partitions in a second memory die of the memory device. The method also includes writing a third codewords to a second set of contiguous partitions in the second memory die of the memory device.

Abstract: A storage system receives a command from a host to overwrite data that is stored in a memory of the storage system. The command may have been issued in error or by malware, so the storage system preserves the data that the host wants to overwrite, just in case the host later wants to recover the data. To do this, the storage system associates the physical address of the location of the memory that stores the data with a logical block address that is inaccessible by the host. To recover the data, the storage system replaces the logical block address that is inaccessible by the host with a logical block address that is accessible by the host.

Abstract: A compressed memory system of a processor-based system includes a memory partitioning circuit for partitioning a memory region into data regions with different priority levels. The system also includes a cache line selection circuit for selecting a first cache line from a high priority data region and a second cache line from a low priority data region. The system also includes a compression circuit for compressing the cache lines to obtain a first and a second compressed cache line. The system also includes a cache line packing circuit for packing the compressed cache lines such that the first compressed cache line is written to a first predetermined portion and the second cache line or a portion of the second compressed cache line is written to a second predetermined portion of the candidate compressed cache line. The first predetermined portion is larger than the second predetermined portion.

Abstract: A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.

Abstract: A processing device and methods of controlling remote persistent writes are provided. Methods include receiving an instruction of a program to issue a persistent write to remote memory. The methods also include logging an entry in a local domain when the persistent write instruction is received and providing a first indication that the persistent write will be persisted to the remote memory. The methods also include executing the persistent write to the remote memory and providing a second indication that the persistent write to the remote memory is completed. The methods also include providing the first and second indications when it is determined not to execute the persistent write according to global ordering and providing the second indication without providing the first indication when it is determined to execute the persistent write to remote memory according to global ordering.