Abstract: A memory adaptive temperature controlling method, a storage device, and a control circuit unit are provided. In this exemplary embodiment, the temperature value is obtained according to the temperature measured by the thermal sensor, and the access speed to be reached is calculated according to the temperature change rate within the specific time range and the adjustment percentage when it is determined that the speed-down or speed-up operation is required to be performed. By adjusting the access speed of the memory storage device in a stepwise manner, the temperature of the memory storage device may be stabilized, thereby striking the balance between the temperature stability and the system performance of the memory storage device.

Abstract: A computing system includes a volatile memory, a cache coupled with the volatile memory, and a processing device coupled with the cache and at least one of a storage device or a network port. The processing device is to: generate a plurality of virtual addresses that are sequentially numbered for data that is to be at least one of processed or transferred in response to an input/output (I/O) request; allocate, for the data, a continuous range of physical addresses of the volatile memory; generate a set of hash-based values based on mappings between the plurality of virtual addresses and respective physical addresses of the continuous range of physical addresses; identify a unique cache line of the cache that corresponds to each respective hashed-based value of the set of hash-based values; and cause the data to be directly stored in the unique cache lines of the cache.

Abstract: A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.

Abstract: A method of controlling a storage device including a command terminal, a plurality of data terminals, and a clock terminal, including receiving a clock signal through the clock terminal; outputting a first status data through the data terminals in accordance with only one of a rising edge and a falling edge of the clock signal in a first transfer mode; outputting data through the data terminals in accordance with both the rising edge and the falling edge of the clock signal in a second transfer mode; and receiving and responding to commands via the command terminal in accordance with only one of a rising edge and a falling edge of the clock signal while outputting data through the data terminals in accordance with both the rising edge and the falling edge of the clock signal in the second transfer mode.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device is DRAM-less. The controller is configured to determine that a connection to a host memory buffer (HMB) of a host device is lost, load a most recent copy of a flash translation layer (FTL) table from the memory device, generate one or more updates to the most recent copy of the FTL table, and re-enable command fetching. The controller is further configured to mark one or more commands in a command database with an error condition upon the determining. After a boot of the connection, the controller is further configured to copy the FTL tables from the memory device to the HMB, work on commands, save FTL table differences between the HMB and the memory device, and update the FTL tables in the memory device.

Abstract: An information processing apparatus including a memory and a memory controller writing data to the memory in response to a write for writing the data to the memory, in which the memory executes error correction processing for each data of a predetermined data length, and the memory controller executes, in place of the memory, read modify write processing in a case where a data length of the data related to the write instruction is smaller than the predetermined data length.

Abstract: A method includes writing a first codeword to a first set of contiguous partitions in a first memory die of a memory device. The method further includes writing a first portion of a second codeword to a second set of contiguous partitions in the first memory die of the memory device and writing a second portion of the second codeword to a first set of contiguous partitions in a second memory die of the memory device. The method also includes writing a third codewords to a second set of contiguous partitions in the second memory die of the memory device.

Abstract: A storage system receives a command from a host to overwrite data that is stored in a memory of the storage system. The command may have been issued in error or by malware, so the storage system preserves the data that the host wants to overwrite, just in case the host later wants to recover the data. To do this, the storage system associates the physical address of the location of the memory that stores the data with a logical block address that is inaccessible by the host. To recover the data, the storage system replaces the logical block address that is inaccessible by the host with a logical block address that is accessible by the host.

Abstract: A compressed memory system of a processor-based system includes a memory partitioning circuit for partitioning a memory region into data regions with different priority levels. The system also includes a cache line selection circuit for selecting a first cache line from a high priority data region and a second cache line from a low priority data region. The system also includes a compression circuit for compressing the cache lines to obtain a first and a second compressed cache line. The system also includes a cache line packing circuit for packing the compressed cache lines such that the first compressed cache line is written to a first predetermined portion and the second cache line or a portion of the second compressed cache line is written to a second predetermined portion of the candidate compressed cache line. The first predetermined portion is larger than the second predetermined portion.

Abstract: A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.

Abstract: A processing device and methods of controlling remote persistent writes are provided. Methods include receiving an instruction of a program to issue a persistent write to remote memory. The methods also include logging an entry in a local domain when the persistent write instruction is received and providing a first indication that the persistent write will be persisted to the remote memory. The methods also include executing the persistent write to the remote memory and providing a second indication that the persistent write to the remote memory is completed. The methods also include providing the first and second indications when it is determined not to execute the persistent write according to global ordering and providing the second indication without providing the first indication when it is determined to execute the persistent write to remote memory according to global ordering.

Abstract: A system is provided. The system includes a solid state storage including a plurality of banks, a first controller that directs one or more commands to a queue of a set of a plurality of queues, and a second controller configured to receive the one or more commands from the plurality of queues. The one or more commands are separated into the set of the plurality of queues based on a command type of each command of the one or more commands, and each set of the plurality of queues includes a first queue configured to store management commands and a second queue configured to store other commands. Each bank of the plurality of banks corresponds to a different set of the plurality of queues. The second controller is configured to generate subcommands based on the commands and direct the subcommands to a bank of the solid state storage.

Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. A first command to write data to a first zone is received, first parity data for the first command is generated in the RAM1, and the data of the first command is written to the first zone. When a second command to write data to a second zone is received, the generated first parity data is copied from the RAM1 to a parking section in the storage unit, and second parity data associated with the second zone is copied from the parking section to the RAM1. The second parity data is then updated in the RAM1 with the data of the second command and copied to the parking section.

Abstract: A counter system includes a counter management subsystem, a storage subsystem having storage elements, and a non-volatile memory system storing a first counter including a first value field/first bitmap field combination for each storage element, and a second counter including a second value field/second bitmap field combination for each storage element. The counter management subsystem resets the first counter and, following each storage operation on a storage element, updates a bit in the first bitmap field for that storage element. When one of the first bitmap fields is filled, the counter management subsystem converts each first value field/first bitmap field combination to a respective first value, resets the second counter, updates the second value field for each storage element with the respective first value for each storage element and, following each storage operation on a storage element, updates a bit in the second bitmap field for that storage element.

Abstract: A method for performing data access performance shaping of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access on the NV memory according to the plurality of host commands; and monitoring the plurality of host commands to control respective performance metrics of a plurality of access control groups of the memory device with a dual-state leaky bucket (LB) model, wherein regarding any access control group, for example: determining at least one first performance metric according to at least one first command to be a first LB fill level of a dual-state LB; in response to the first LB fill level being below a state threshold, determining the dual-state LB to be in a first predetermined state, and configuring the dual-state LB to have a first predetermined drain rate, for dynamically adjusting performance quota.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a connection to a host memory buffer (HMB) of a host device is lost, load a most recent copy of a flash translation layer (FTL) table from the memory device, generate one or more updates to the most recent copy of the FTL table, and re-enable command fetching. The controller is further configured to mark one or more commands in a command database with an error condition upon the determining. After a boot of the connection, the controller is further configured to copy the FTL tables from the memory device to the HMB, work on commands, save FTL table differences between the HMB and the memory device, and update the FTL tables in the memory device.

Abstract: Various embodiments provide for one or more processor instructions and memory instructions that enable a memory sub-system to copy, move, or swap data across (e.g., between) different memory tiers of the memory sub-system, where each of the memory tiers is associated with different memory locations (e.g., different physical memory locations) on one or more memory devices of the memory sub-system.

Abstract: According to one embodiment, when data is to be written to a first physical storage location that is designated by a first physical address, a memory system encrypts the data with the first physical address and a first encryption key, and writes the encrypted data to the first physical storage location. When the encrypted data is to be copied to a second physical storage location, the memory system decrypts the encrypted data with the first physical address and the first encryption key, and re-encrypts the decrypted data with a second encryption key and a copy destination physical address indicative of the second physical storage location.

Abstract: A memory system includes a memory device including plural memory blocks and a controller configured to perform garbage collection on a victim block among the plural memory blocks. The controller is further configured to stop the garbage collection in response to an interrupt and invalidate a valid data item, which is copied from the victim block to a target block during the garbage collection.

Abstract: Devices and techniques for efficient obfuscated logical-to-physical mapping are described herein. For example, activity corresponding to obfuscated regions of an L2P map for a memory device can be tracked. A record of discontinuity between the obfuscated regions and L2P mappings resulting from the activity can be updated. The obfuscated regions can be ordered based on a level of discontinuity from the record of discontinuity. When an idle period is identified, an obfuscated region from the obfuscated regions is selected and refreshed based on the ordering.