Patents Examined by Ryan Dare
  • Patent number: 10353637
    Abstract: A method and system for use in managing data storage is disclosed. Data storage in a data storage system is managed. The data storage system comprises a first cache and at least one solid state drive for storing data. The data storage in connection with the at least one solid state drive is monitored. The amount of free data storage capacity in connection with the at least one solid state drive is determined in response to monitoring the data storage in connection with the at least one solid state drive. At least a portion of the free data storage capacity is provisioned as a second cache in response to determining the amount of free data storage capacity in connection with the at least one solid state drive.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 16, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Phillip P Fultz, Kiran Prakash Madnani, Manpreet Singh
  • Patent number: 10346079
    Abstract: A method of managing snapshots on a storage system includes a storage controller (1) receiving a request to store a first snapshot associated with a first volume among a plurality of volumes on the storage system and (2) determining if an assigned snapshot reserve space remaining associated with the first volume is less than an amount of space that is required to store the first snapshot. In response to the assigned snapshot reserve space remaining being less than the amount of space required, borrowing snapshot reserve space from at least one of an unused assigned space or an unused unassigned space within the storage system and storing at least a portion of the first snapshot to the borrowed snapshot reserve space.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 9, 2019
    Assignee: Dell Products, L.P.
    Inventors: Eric Robert Schott, Nishant Kanaiyalal Mehta, Timothy D. Nolan, Paul Anthony Calato, Shari Ann Vietry
  • Patent number: 10326588
    Abstract: Aspects of the disclosure relate to ensuring information security in data transfers by dividing and encrypting data blocks. A computing platform may receive, from a data source computing device, a source data collection for a secure physical-storage-media data transfer and may identify one or more transmission parameters associated with the secure physical-storage-media data transfer. Subsequently, the computing platform may divide the source data collection into two or more data blocks and may separately encrypt the two or more data blocks based on the one or more transmission parameters to produce two or more encrypted data blocks for the secure physical-storage-media data transfer. Then, the computing platform may store the two or more encrypted data blocks on two or more physical media, and each encrypted data block of the two or more encrypted data blocks may be stored on a different physical medium of the two or more physical media.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 18, 2019
    Assignee: Bank of America Corporation
    Inventors: Manu Kurian, Sorin N. Cismas
  • Patent number: 10324634
    Abstract: A memory device having a memory array and a controller operably coupled to the memory array is described. The controller is configured to store a sketch comprising d rows and w columns, wherein d and w are positive integers. Each row corresponds to a different one of d hash functions. The controller is also configured to detect an event associated with a memory address and to hash the memory address with each of the d hash functions to generate a corresponding d sketch locations. The controller is further configured, for each of the d sketch locations, to set a detection window flag, if it is not already set, and to adjust a stored sketch value by an amount corresponding to the event. The controller is also configured to evaluate a summary metric corresponding to the stored sketch value in each of the d sketch locations to determine if a threshold value has been reached.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Samuel E. Bradshaw
  • Patent number: 10318177
    Abstract: A method includes creating multiple logical compartments in a data storage device to hold respective multiple portions of an ordered list of elements, encapsulating each element, of a portion for each compartment, in a node with pointers to successive nodes in the portion, creating a set of references to a first node in each compartment, and providing a count of the number of elements in each compartment.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: June 11, 2019
    Assignee: SAP SE
    Inventor: Arjun Krishnakumar
  • Patent number: 10310748
    Abstract: This specification describes methods, systems, and computer program products for maintaining data representing where each data block of multiple data blocks are stored among multiple computing nodes. Each computing node generates a respective locality summary based on locally stored data blocks, and submits the locality summary to a controlling computing node.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: June 4, 2019
    Assignee: Pivotal Software, Inc.
    Inventors: Harshad Deshmukh, Adalbert Gerald Soosai Raj, Jignesh M. Patel
  • Patent number: 10296480
    Abstract: A data processing system includes a central processing unit (CPU), a control block configured to interface with the CPU, a cache memory configured to interface with the control block and arranged to be spaced from the CPU by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the CPU by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells. The working memory is allocated to one memory layer selected among the plurality of memory layers. The storage memory is allocated to remaining memory layers among the plurality of memory layers.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Sung Cheoul Kim, Tae Ho Kim
  • Patent number: 10289569
    Abstract: An illegal address access blocking circuit includes a first register and a second register to set upper and lower limit values of an address range within which access to an external device is allowed. A first comparator compares a first value and the upper limit value, and outputs a high level signal when the first value is larger than the upper limit value. A second comparator compares the first value and the lower limit value, and outputs a low level signal. A first and logic circuit holds a logic sum of the high and low level signals, and outputs the logic sum as a third output, and a second logic circuit compares a fourth value inputted to a first request control line and the third output, and outputs a result of the comparison to a second request control line.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: May 14, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Yuki Kondoh
  • Patent number: 10289349
    Abstract: A local storage device (LSD) is provided configured to have a host device (HD) in communication with the LSD. The LSD includes a memory array. The LSD is configured to characterize data access usage of the LSD by at least one program executing on the HD. The LSD is configured to monitor access to the LSD as a result of data access operations by the HD relative to the memory array of the LSD. The LSD is additionally configured to determine characteristics of the monitored access. The LSD is additionally configured to, based on characteristics of the monitored access, determine and store data on the LSD indicative of the characterized monitored access.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: May 14, 2019
    Assignee: SanDisk IL, LTD.
    Inventors: Alain Nochimowski, Micha Rave, Itzhak Pomerantz, Eitan Mardiks
  • Patent number: 10268400
    Abstract: A non-volatile memory system may include a controller configured for parsing a host file system, identifying a location of a host file system directory and tracking directory entries of files deleted from the host file system directory but having valid data mappings in the logical-to-physical mapping table. The controller may then store the location of the host file system directory, monitor activity in the host file system directory and track validity status information for use in optimizing a compaction process. The compaction process may include segregating into separate compaction destination blocks valid data based on the stored validity status such that data valid in both the host file system directory and the logical-to-physical mapping table is in compaction destination blocks separate from data having valid logical-to-physical mapping entries but associated with deleted host file system directory entries.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: April 23, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Narendhiran Chinaaanangur Ravimohan, Muralitharan Jayaraman
  • Patent number: 10268598
    Abstract: A counter of a primary memory module provides a count indicative of the number of times the primary memory module has ever been read/written by a processor. With the count, an operating mode of the primary memory module is evaluated to optimize memory allocation performed by the data processing system, adjust the operating mode of the primary memory module, and send a warning message to a user, for example.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chang Li Ping, Alpus P. Chen, Chun-Wei Chen, Elysee Hsieh, Kelvin Shieh, Wei-Chin Tsai
  • Patent number: 10241692
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. For example, the computing device monitors storage unit (SU)-based write transfer rates and SU-based write failure rates associated with each of the SUs for a write request of encoded data slices (EDSs) to the SUs within the DSN. The computing device generates and maintains a SU write performance distribution based on monitoring of the SU-based write transfer rates and the SU-based write failure rates and adaptively adjusts a trimmed write threshold number of EDSs and/or a target width of EDSs for write requests of sets of EDSs to the SUs within the DSN.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg R. Dhuse, Jason K. Resch, Ethan S. Wozniak
  • Patent number: 10235290
    Abstract: Systems, apparatuses, and methods for sorting memory pages in a multi-level heterogeneous memory architecture. The system may classify pages into a first “hot” category or a second “cold” category. The system may attempt to place the “hot” pages into the memory level(s) closest to the systems' processor cores. The system may track parameters associated with each page, with the parameters including number of accesses, types of accesses, power consumed per access, temperature, wearability, and/or other parameters. Based on these parameters, the system may generate a score for each page. Then, the system may compare the score of each page to a threshold. If the score of a given page is greater than the threshold, the given page may be designated as “hot”. If the score of the given page is less than the threshold, the given page may be designated as “cold”.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 19, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Blagodurov, Gabriel H. Loh, Mitesh R. Meswani
  • Patent number: 10216484
    Abstract: A system on chip (SoC) may include a nonvolatile ferroelectric random access memory (FRAM). A random number may be created by applying operating power to the ferroelectric random access memory (FRAM) device and reading a sequence of virgin memory locations within the FRAM device to produce the random number sequence. The sequence of virgin memory locations had previously never been written. The random number may be produced during an initial boot of the SoC, for example. Alternatively, the random number may be saved by a test station during testing of the FRAM device after fabrication of the FRAM device. A memory test of the FRAM may then be performed, after which the random number may be stored in a defined location in the FRAM.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: February 26, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Eric Thierry Peeters, William Francis Kraus, Manuel Gilberto Aguilar, John Anthony Rodriguez
  • Patent number: 10216585
    Abstract: Systems and methods for enabling disk image operations in conjunction with snapshot locking. An example method may include: attaching a first snapshot to a first virtual machine the first snapshot being stored within a disk image, generating, in view of the first snapshot, a second snapshot, the second snapshot being stored within the disk image, attaching the first snapshot to a second virtual machine, and causing the first snapshot to be locked in view of the second virtual machine performing one or more operations on the first snapshot, wherein the first virtual machine performs one or more operations on the second snapshot concurrent with the locking of the first snapshot.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: February 26, 2019
    Assignee: Red Hat Israel, Ltd.
    Inventor: Liron Aravot
  • Patent number: 10198370
    Abstract: A system, methods, and apparatus for determining memory distribution across multiple non-uniform memory access processing nodes are disclosed. An apparatus includes processing nodes, each including processing units and main memory serving as local memory. A bus connects the processing units of each processing node to different main memory of a different processing node as shared memory. Access to local memory has lower memory access latency than access to shared memory. The processing nodes execute threads distributed across the processing nodes, and detect memory accesses made from each processing node for each thread. The processing nodes determine locality values for the thread that represent the fraction of memory accesses made from the processing nodes, and determine processing time values for the threads for a sampling period. The processing nodes determine weighted locality values for the threads, and determine a memory distribution across the processing nodes based on the weighted locality values.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: February 5, 2019
    Assignee: Red Hat, Inc.
    Inventor: Henri van Riel
  • Patent number: 10198191
    Abstract: A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: February 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takafumi Ito
  • Patent number: 10198197
    Abstract: A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: February 5, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventor: Yiren Huang
  • Patent number: 10191815
    Abstract: Techniques to back up a cluster shared volume (CSV) are disclosed. In various embodiments, a snapshot of the cluster shared volume is stored persistently on the cluster shared volume itself. A task to back up a corresponding assigned portion of the snapshot is assigned to each of one or more cluster servers available to participate in backing up the cluster shared volume. The cluster servers have shared access to the snapshot as stored on the cluster shared volume, and each is configured to perform the task assigned to it in parallel with any other cluster servers assigned to back up other portions of the same cluster shared volume snapshot. The respective assigned tasks are monitored to completion.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: January 29, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Sathyamoorthy Viswanathan, Ajith Gopinath, Kishore Kumar
  • Patent number: 10185514
    Abstract: A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: January 22, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Thomas Fahrig