Abstract: A hybrid addressing scheme in which a maximum of three codeword groups are utilized across pairs of memory dice and/or access rows of the memory sub-system or memory device is provided. By controlling the arrangement of such codewords, it can be possible to group codewords such that disturb effects can be reduced. For example, codewords can be grouped in a symmetrical manner with respect to the memory dice of a memory device, which can allow for simplified codeword addressing.

Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

Abstract: Examples described herein include systems and methods which include an apparatus comprising a memory array including a plurality of memory cells and a memory controller coupled to the memory array. The memory controller comprises a memory mapper configured to configure a memory map on the basis of a memory command associated with a memory access operation. The memory map comprises a specific sequence of memory access instructions to access at least one memory cell of the memory array. For example, the specific sequence of memory access instructions for a diagonal memory command comprises a sequence of memory access instructions that each access a memory cell along a diagonal of the memory array.

Abstract: Compressibility instrumented dynamic volume provisioning is disclosed. For example, a plurality of storage pools includes first and second storage pools, and is managed by a storage controller that receives a request to provision a first persistent storage volume associated with a first container, where the first storage pool has a first storage configuration including a deduplication setting, a compression setting, and/or an encryption setting. The first persistent storage volume is created in the first storage pool based on a first storage mode stored in metadata associated with the first container, where the storage mode includes a deduplication mode, a compression mode, and/or an encryption mode. A second persistent storage volume is in the second storage pool with a second storage configuration different from the first storage configuration based on a second storage mode associated with a second container.

Abstract: An apparatus, system, and method are disclosed for efficiently managing commands in a solid-state storage device that includes a solid-state storage arranged in two or more banks. Each bank is separately accessible and includes two or more solid-state storage elements accessed in parallel by a storage input/output bus. The solid-state storage includes solid-state, non-volatile memory. The solid-state storage device includes a bank interleave that directs one or more commands to two or more queues, where the one or more commands are separated by command type into the queues. Each bank includes a set of queues in the bank interleave controller. Each set of queues includes a queue for each command type. The bank interleave controller coordinates among the banks execution of the commands stored in the queues, where a command of a first type executes on one bank while a command of a second type executes on a second bank.

Abstract: Devices and techniques for efficient obfuscated logical-to-physical mapping are described herein. For example, activity corresponding to obfuscated regions of an L2P map for a memory device can be tracked. A record of discontinuity between the obfuscated regions and L2P mappings resulting from the activity can be updated. The obfuscated regions can be ordered based on a level of discontinuity from the record of discontinuity. When an idle period is identified, an obfuscated region from the obfuscated regions is selected and refreshed based on the ordering.

Abstract: A method of controlling a storage device attached to a host device, includes transferring data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal in first and second transfer modes. In response to a check function command, status data indicating that the storage device supports the second transfer mode is output through a data terminal. In response to a set function command, the storage device is set into the second transfer mode. The check function and the set function are switched in response to a first value and a second value of a mode bit in the check function command.

Abstract: The invention relates to methods, and an apparatus for data reads in a host performance acceleration (HPA) mode. One method is performed by a host side to include: issuing a switch command to a flash controller to request the flash controller to activate an HPA function, and an acquisition function for a logical-block-address to physical-block-address (L2P) mapping table; issuing a write_multiple_block command to the flash controller to transfer a data block to a flash controller, where the data block includes a region number and a sub-region number; issuing a read_multiple_block command to the flash controller to obtain a plurality of L2P mapping entries corresponding to the region number and the sub-region number from the flash controller. The host side and the flash controller communicate with each other in an embedded multi-media card (eMMC) protocol.

Abstract: The invention relates to methods, and an apparatus for data reads in a host performance acceleration (HPA) mode. One method is performed by a host side to include: searching an HPA buffer in a system memory for a logical-block-address to physical-block-address (L2P) mapping entry corresponding to a logical block address (LBA); issuing a switch command to a flash controller to request the flash controller to activate an HPA function, and does not activate an acquisition function for an L2P mapping table, where the host side and the flash controller communicate with each other in an embedded multi-media card (eMMC) protocol; issuing a write_multiple_block command to the flash controller to transfer a first data block to the flash controller, which includes the first L2P mapping entry; and issuing a read_multiple_block command to obtain data corresponding to the first L2P mapping entry from the flash controller.

Abstract: A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.

Abstract: There is provided a parallel processing device which allows consecutive parallel data processing to be performed. The parallel processing device includes: a plurality of addition units configured to selectively receive input data among output data from the plurality of input units according to configuration values for each addition unit of the plurality of addition units, and perform addition operation for the input data in parallel; and the plurality of the delay units configured to delay input data for one cycle. Each delay unit of the plurality of the delay units delays output data from each addition unit of the plurality of addition units and outputs the delayed output data to each input unit of the plurality of input units.

Abstract: According to one embodiment, when data is to be written to a first physical storage location that is designated by a first physical address, a memory system encrypts the data with the first physical address and a first encryption key, and writes the encrypted data to the first physical storage location. When the encrypted data is to be copied to a second physical storage location, the memory system decrypts the encrypted data with the first physical address and the first encryption key, and re-encrypts the decrypted data with a second encryption key and a copy destination physical address indicative of the second physical storage location.

Abstract: A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.

Abstract: Memory allocation circuitry allocate a memory region in memory, and bounded pointer generation circuitry generates bounded pointers including a revocable bounded pointer that provides a pointer value and range information identifying an address range of the memory region. The memory allocation circuitry provides, at a header location in the memory, a header for the memory region with a first token field which is initialized to a first token value associated with the memory region. The memory allocation circuitry is responsive to the deallocation of the memory region to modify the stored value in the first token field of the header. In response to a request to generate a memory address using the revocable bounded pointer, a use authentication check prevents generation of the memory address when it is determined that the stored value in the first token field has been changed.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method comprises: sending a read command to the flash memory module to ask for data on at least one memory unit; and analyzing state information of a plurality of memory cells of the memory unit based on information from the flash memory module to determine a decoding method adopted by a decoder.

Abstract: The present invention provides an electronic device, wherein the electronic device includes a flash memory module and a flash memory controller. The flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the flash memory controller is configured to access the flash memory module. In the operations of the electronic device, when the flash memory controller sends a read command to the flash memory module to ask for data on at least one page, the flash memory module uses a plurality of read voltages to read each memory cell of the at least one page to obtain multi-bit information of each memory cell, and the flash memory module transmits the multi-bit information of each memory cell of the at least one page to the flash memory controller.

Abstract: A memory system includes a storage medium having a plurality of memory regions. A controller is configured to allocate each of a plurality of open memory regions among the memory regions to one or more levels and store, in response to a write request received from a host device that includes data and a level of the data, the data in an open memory region allocated to the level. A level may be a level of a file in a predetermined unit in which the data is included, such as in a log-structured merge (LSM) tree structure.

Abstract: Described are methods and systems for improved cardinality estimation. A method may include obtaining a data-query, obtaining a row, generating a hash value, determining a cardinality of leading zeros in the hash value, identifying a bucket with respect to the hash value, including a bucket identifier and the cardinality of leading zeros in a representation, determining the approximate unique count, and outputting the approximate unique count as results data responsive to the portion of the data-query.

Abstract: In one aspect, a device may include at least one processor and storage accessible to the at least one processor. The storage may include instructions executable by the at least one processor to allocate, in memory, a read-once memory container to store data from a first computer program. The instructions may also be executable to write the data from the first computer program to the read-once memory container and to permit a second computer program to use the data as stored in the read-once memory container. The data, upon being accessed from the read-once memory container, may not be readable again from the read-once memory container without being written again.

Abstract: Method for reducing memory fragmentation characterized in that it the steps of: for each image in a source set of images (601) determining image size (602) in pixels and obtaining (603) a minimal total number of pixels for an aggregated surface by obtaining a sum of image sizes; factorizing (604) the sum of image sizes into a surface's width and height; allocating memory (702) for the surface (701); creating (703) a mapping between an image identifier and its location, width, height for each image associated with the surface; for each image, according to its offset in the surface, the two-dimensional space of the image is cast (704) to one dimension; knowing the casting formula between the one and two-dimensional spaces, copying each image to the surface (705).