Abstract: There are provided a controller, a memory system having the same, and an operating method thereof. The controller includes: a host interface configured to receive a format request from a host, and output an internal format request including initial logical unit information; and a flash translation layer configured to initialize a map table for storing information on mapping between logical and physical unit numbers according to the initial logical unit information.

Abstract: Embodiments of the invention utilize an improved LSM-tree-based key-value approach to strike the optimal balance between the costs of updates and lookups and storage space. The improved approach involves use of a new merge policy that removes merge operations from all but the largest levels of LSM-tree. In addition, the improved approach may include an improved LSM-tree that allows separate control over the frequency of merge operations for the largest level and for all other levels. By adjusting various parameters, such as the storage capacity of the largest level, the storage capacity of the other smaller levels, and/or the size ratio between adjacent levels in the improved LSM-tree, the improved LSM-tree-based key-value approach may maximize throughput for a particular workload.

Abstract: The present invention provides a decoding method, a memory controlling circuit unit, and a memory storage device. The decoding method includes: receiving a plurality of commands; reading a first physical programming unit to obtain a plurality of first data respectively by using a plurality of first reading voltage groups of a plurality of reading voltage groups based on a first read command of the plurality of commands and executing a first decoding operation in each of the plurality of first data, wherein a number of the plurality of first reading voltage groups is less than a number of the plurality of reading voltage groups; and executing other commands being different from the first read command of the plurality of commands when unsuccessfully executing the first decoding operation for each of the plurality of first data.

Abstract: In one embodiment, a method for managing overprovisioning in a solid state storage drive array comprises receiving usage data from each of a plurality of solid state storage drives, determining a predicted service life value for each of the plurality of solid state storage drives based on at least the usage data, comparing each of the predicted service life values with a predetermined service life value for each respective solid state storage drive, and dynamically adjusting an available logical storage capacity for at least one of the plurality of solid state storage drives based on a result of the step of comparing.

Abstract: A technique is provided which can facilitate management of data in a memory device in a semiconductor device including the memory device and a data processing device. The semiconductor device includes a first external terminal, a second external terminal, a data processing device, and a memory device. The semiconductor device further includes a first bus coupled between the data processing device and the memory device, a second bus coupled between the data processing device and the second external terminal, a third bus coupled to the first external terminal, and a control circuit coupled to the first bus and the third bus. The control circuit has a management function of the memory device using the third bus.

Abstract: The present application provides methods and systems for memory management of a kernel space and a user space. An exemplary system for memory management of the kernel space and the user space may include a first storing unit configured to store a first root page table index corresponding to the kernel space. The system may also include a second storing unit configured to store a second root page table index corresponding to the user space. The system may further include a control unit communicatively coupled to the first and second registers and configured to: translate a first virtual address to a first physical address in accordance with the first root page table index for an operating system kernel, and translate a second virtual address to a second physical address in accordance with the second root page table index for a user process.

Abstract: Methods, systems, and devices for codeword rotation for zone grouping of media codewords are described. A value of a first pointer may be configured to correspond to a first memory address within a region of memory and a value of a second pointer may be configured to correspond to a second memory address within the region of memory. The method may include monitoring access commands for performing access operations within the region of memory, where the plurality of access command may be associated with requested addresses within the region of memory. The method may include updating the value of the second pointer bases on a quantity of the commands that are monitored satisfying a threshold and executing the plurality of commands on locations within the region of memory. The locations may be based on the requested address, the value of the first pointer, and the value of the second pointer.

Abstract: The present disclosure includes apparatuses and methods for shift decisions. An example apparatus includes a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes a sense amplifier and a compute component coupled to a sense line and configured to implement logical operations and a decision component configured to implement a shift of data based on a determined functionality of a memory cell in the array.

Abstract: A memory of an electronic device includes a first memory region and a second memory region. A memory allocation method includes: receiving a request for memory allocation, the request for memory allocation including a memory capacity to be allocated; comparing the memory capacity to be allocated and a capacity range of a preset memory block to obtain a comparison result; according to the comparison result, allocating a memory block with the memory capacity from at least one of the first memory region or the second memory region.

Abstract: A processing device comprises an address translation circuit to intercept a work request from an I/O device. The work request comprises a first ASID to map to a work queue. A second ASID of a host is allocated for the first ASID based on the work queue. The second ASID is allocated to at least one of: an ASID register for a dedicated work queue (DWQ) or an ASID translation table for a shared work queue (SWQ). Responsive to receiving a work submission from the SVM client to the I/O device, the first ASID of the application container is translated to the second ASID of the host machine for submission to the I/O device using at least one of: the ASID register for the DWQ or the ASID translation table for the SWQ based on the work queue associated with the I/O device.

Abstract: A data storage device includes at least one non-volatile memory and a controller with two-layer architecture. The two-layer architecture includes a front end coupled to a host and a back end coupled to the non-volatile memory. The controller includes a command processor and at least one non-volatile memory controller. The command processor is arranged on the front end to communicate with the host, and it schedules the operation of the data storage device based on an external command from the host. The non-volatile memory controller is arranged on the back end, and it controls the non-volatile memory based on the schedule of the command processor. When the non-volatile memory increases, the non-volatile memory controller also increases correspondingly while the amount of command processors remains the same.

Abstract: A cache management method for a computing device, a cache controller, a processor and a processor readable storage medium are disclosed. The cache management method for the computing device includes classifying a workload on a cache based on a cache architecture of the computing device, characteristics of a cache level of the cache and a difference in the workload on the cache, and configuring a priority for the classified workload; and allocating a cache resource and performing cache management according to the configured priority.

Abstract: Examples include techniques to prefetch data from a second level of memory of a hierarchical arrangement of memory to a second level of memory of the hierarchical arrangement of memory. Examples include circuitry for a processor receiving a prefetch request from a core of the processor to prefetch data from the first level to the second level. The prefetch request indicating an amount of data to prefetch that is greater than a data capacity of a cache line utilized by the core.

Abstract: The present invention provides an electronic device, wherein the electronic device includes a flash memory module and a flash memory controller. The flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the flash memory controller is configured to access the flash memory module. In the operations of the electronic device, when the flash memory controller sends a read command to the flash memory module to ask for data on at least one page, the flash memory module uses a plurality of read voltages to read each memory cell of the at least one page to obtain multi-bit information of each memory cell, and the flash memory module transmits the multi-bit information of each memory cell of the at least one page to the flash memory controller.

Abstract: In a method for deleting a cascaded snapshot, a storage device includes a logical volume corresponding to a plurality of cascaded snapshots. The plurality of cascaded snapshots comprises at least a first snapshot, a second snapshot, and a third snapshot. The second snapshot is a parent snapshot of the first snapshot, the third snapshot being a child snapshot of the first snapshot. The storage device receives an instruction for deleting the first snapshot. The first snapshot comprises target data. The storage device migrates information of the target data to the second snapshot. Further, the storage device sets a parent snapshot identifier corresponding to the third snapshot to an identifier of the second snapshot, and deletes the first snapshot.

Abstract: Systems and methods are disclosed for monitoring power usage and temperature within a data storage device, and adjusting performance based on the power usage and temperature. In certain embodiments, an apparatus may comprise a data storage device (DSD) having an interface to communicate with a host device, and a circuit. The circuit may be configured to receive a first limit designation for a first operating parameter of the DSD via the interface, monitor a value of the first operating parameter of the DSD, evaluate a pending workload of operations to be performed by the DSD, estimate a future value of the first operating parameter based on the pending workload, and adjust performance of the DSD based on the future value and the first limit designation.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method comprises: sending a read command to the flash memory module to ask for data on at least one memory unit; and analyzing state information of a plurality of memory cells of the memory unit based on information from the flash memory module to determine a decoding method adopted by a decoder.

Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.

Abstract: A method, computer program product, and system includes a processing circuit(s) allocating a page of system memory address space to a device. The allocating includes the processing circuits(s) obtaining base address registers of the device in a bus and determining a portion of the page of the system memory address space to allocate to the base address registers. The processing circuits(s) sorts the base address registers, in a descending order, according to their alignments and adds sizes of the sorted base address registers to determine the portion of the page. The processing circuit(s) determines a remainder of the page: a difference between a size of the page and the portion of the page. The processing circuit(s) requests a virtual resource of a size equal to the remainder and allocates the page to the sorted base address registers and to the virtual resource.

Abstract: A system and method for efficiently handling maintenance requests among multiple processors. In various embodiments, a given processor of multiple processors receives a maintenance request. If maintenance requests are not currently being blocked, then the given processor determines a type of the maintenance request and updates one or more maintenance type counters based on the type. If one or more counters exceed a threshold, an indication is generated specifying maintenance requests received at a later time are to be held. The received maintenance request is processed. Different types of maintenance requests are used for invalidating entries in the instruction cache, for invalidating entries in a TLB and for synchronizing page table updates. Afterward, software applications continue processing. Forward progress of the software applications is measured using one or more metrics. If forward progress has been achieved, then one or more maintenance type counters are reset.