Patents Examined by Ryan Dare
  • Patent number: 10497424
    Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yu-Feng Chen, Byung S. Moon, Myung Ho Bae, Harish N. Venkata
  • Patent number: 10496544
    Abstract: In one embodiment, aggregated write back in a direct mapped two level memory in accordance with the present description, aggregates a dirty block or other subunit of data being evicted from a near memory of a two level memory system, with other spatially co-located dirty subunits of data in a sector or other unit of data for write back to a far memory of the two level memory system. In one embodiment, dirty spatially co-located subunits are scrubbed and aggregated with one or more spatially co-located dirty subunits being evicted. In one embodiment, a write combining buffer is utilized to aggregate spatially co-located dirty subunits prior to being transferred to a far memory write buffer in a write back operation. Other aspects are described herein.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Zhe Wang, Christopher B. Wilkerson, Zeshan A. Chishti
  • Patent number: 10496523
    Abstract: An example method includes determining a configuration of two or more partitions for a sequential access medium. At least one partition stores data de-duplication data structures while at least one other partition stores a repository of unique data blocks associated with the data structures. The method also includes controlling a data de-duplication computer to configure the sequential access medium according to the configuration. The method includes producing an output sequence for writing the data structures and a set of unique data blocks associated with the set of data structures to the sequential access medium as configured with the two or more partitions. One embodiment includes controlling a data de-duplication computer to write the data de-duplication data structures and the set of unique data blocks to the sequential access medium according to the output sequence.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: December 3, 2019
    Assignee: Quantum Corporation
    Inventor: Roderick B. Wideman
  • Patent number: 10474385
    Abstract: Systems, devices, and methods for managing fragmentation in hardware-assisted compression of data in physical computer memory which may result in reduced internal fragmentation. An example computer-implemented method comprises: providing, by a memory management program to compression hardware, a compression command including an address in physical computer memory of data to be compressed and a list of at least two available buffers for storing compressed data; using, by the compression hardware, the address included in the compression command to retrieve uncompressed data; compressing the uncompressed data; and selecting, by the compression hardware, from the list of at least two available buffers, at least two buffers for storing compressed data based on an amount of space that would remain if the compressed data were stored in the at least two buffers, wherein each of the at least two selected buffers differs in size from at least one other of the selected buffers.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: November 12, 2019
    Assignee: Google LLC
    Inventors: Santhosh Rao, Sameer Nanda, Vyacheslav Vladimirovich Malyugin, Luigi Semenzato, Aaron Durbin, Keith Robert Pflederer, Hsiao-Heng Kelin Lee, Rahul Jagdish Thakur
  • Patent number: 10452282
    Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Preston A. Thomson, Renato C. Padilla, Ashutosh Malshe
  • Patent number: 10402103
    Abstract: Techniques to optimize use of the available capacity of a backup target storage device are disclosed. In various embodiments, a current capacity of a target system to which backup data is to be streamed to handle additional streams is determined dynamically, at or near a time at which a backup operation is to be performed. One or more backup parameters of the backup operation is/are set dynamically, based at least in part on the dynamically determined current capacity of the target system.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: September 3, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Shelesh Chopra, Rajkumar Palkhade
  • Patent number: 10380068
    Abstract: Example apparatus and methods reserve space in a journal using an observation based approach instead of a fixed sized approach or a worst case scenario approach. One example method receives a request to allocate space in a journal to support a file system transaction. The example method reserves an amount of space in the journal based on a pre-existing reservation size estimate. Unlike conventional systems, the estimate is not based on a worst-case scenario. The example method observes the actual amount of storage used in the journal by the file system transaction and then selectively automatically adjusts the pre-existing reservation size estimate. The estimate may slowly shrink if no overflows are encountered but may quickly grow if an overflow is detected.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: August 13, 2019
    Assignee: Quantum Corporation
    Inventor: Stephen P. Lord
  • Patent number: 10379757
    Abstract: A memory device having a memory array with a plurality of memory addresses and a controller operably coupled to the memory array is described. The controller is configured to store a sketch comprising d rows and w columns, wherein d and w are positive integers. Each of the d rows corresponds to a different one of d hash functions. The controller is also configured to detect an event associated with a first memory address of the plurality of memory addresses and to hash the first memory address with each of the d hash functions to generate a corresponding d sketch locations. The controller is further configured to adjust, for each of the d sketch locations, a stored sketch value by a first amount corresponding to the event.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Samuel E. Bradshaw
  • Patent number: 10365844
    Abstract: Provided are an apparatus, method, and system for logical block address to physical block address (L2P) compression. In response to a physical block address (PBA) of a first indirection unit (IU) among a plurality of IUs in a compression unit being updated, it is determined whether IU data of the plurality of IUs is compressible. In response to determining that the IU data is compressible, one or more contiguous IU groups in the compression unit that are compressible are identified based on corresponding PBAs and, then, a compression unit descriptor and PBAs for unique IUs of the plurality of IUs are written into the compression unit. In response to determining that the IU data is incompressible, a flag indicating that IU data is incompressible, PBAs for some of the IUs, and a pointer to PBAs of remaining IUs are written into the compression unit.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: July 30, 2019
    Assignee: INTEL CORPORATION
    Inventors: Peng Li, Sanjeev N. Trika
  • Patent number: 10353637
    Abstract: A method and system for use in managing data storage is disclosed. Data storage in a data storage system is managed. The data storage system comprises a first cache and at least one solid state drive for storing data. The data storage in connection with the at least one solid state drive is monitored. The amount of free data storage capacity in connection with the at least one solid state drive is determined in response to monitoring the data storage in connection with the at least one solid state drive. At least a portion of the free data storage capacity is provisioned as a second cache in response to determining the amount of free data storage capacity in connection with the at least one solid state drive.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 16, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Phillip P Fultz, Kiran Prakash Madnani, Manpreet Singh
  • Patent number: 10346079
    Abstract: A method of managing snapshots on a storage system includes a storage controller (1) receiving a request to store a first snapshot associated with a first volume among a plurality of volumes on the storage system and (2) determining if an assigned snapshot reserve space remaining associated with the first volume is less than an amount of space that is required to store the first snapshot. In response to the assigned snapshot reserve space remaining being less than the amount of space required, borrowing snapshot reserve space from at least one of an unused assigned space or an unused unassigned space within the storage system and storing at least a portion of the first snapshot to the borrowed snapshot reserve space.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 9, 2019
    Assignee: Dell Products, L.P.
    Inventors: Eric Robert Schott, Nishant Kanaiyalal Mehta, Timothy D. Nolan, Paul Anthony Calato, Shari Ann Vietry
  • Patent number: 10326588
    Abstract: Aspects of the disclosure relate to ensuring information security in data transfers by dividing and encrypting data blocks. A computing platform may receive, from a data source computing device, a source data collection for a secure physical-storage-media data transfer and may identify one or more transmission parameters associated with the secure physical-storage-media data transfer. Subsequently, the computing platform may divide the source data collection into two or more data blocks and may separately encrypt the two or more data blocks based on the one or more transmission parameters to produce two or more encrypted data blocks for the secure physical-storage-media data transfer. Then, the computing platform may store the two or more encrypted data blocks on two or more physical media, and each encrypted data block of the two or more encrypted data blocks may be stored on a different physical medium of the two or more physical media.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 18, 2019
    Assignee: Bank of America Corporation
    Inventors: Manu Kurian, Sorin N. Cismas
  • Patent number: 10324634
    Abstract: A memory device having a memory array and a controller operably coupled to the memory array is described. The controller is configured to store a sketch comprising d rows and w columns, wherein d and w are positive integers. Each row corresponds to a different one of d hash functions. The controller is also configured to detect an event associated with a memory address and to hash the memory address with each of the d hash functions to generate a corresponding d sketch locations. The controller is further configured, for each of the d sketch locations, to set a detection window flag, if it is not already set, and to adjust a stored sketch value by an amount corresponding to the event. The controller is also configured to evaluate a summary metric corresponding to the stored sketch value in each of the d sketch locations to determine if a threshold value has been reached.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Samuel E. Bradshaw
  • Patent number: 10318177
    Abstract: A method includes creating multiple logical compartments in a data storage device to hold respective multiple portions of an ordered list of elements, encapsulating each element, of a portion for each compartment, in a node with pointers to successive nodes in the portion, creating a set of references to a first node in each compartment, and providing a count of the number of elements in each compartment.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: June 11, 2019
    Assignee: SAP SE
    Inventor: Arjun Krishnakumar
  • Patent number: 10310748
    Abstract: This specification describes methods, systems, and computer program products for maintaining data representing where each data block of multiple data blocks are stored among multiple computing nodes. Each computing node generates a respective locality summary based on locally stored data blocks, and submits the locality summary to a controlling computing node.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: June 4, 2019
    Assignee: Pivotal Software, Inc.
    Inventors: Harshad Deshmukh, Adalbert Gerald Soosai Raj, Jignesh M. Patel
  • Patent number: 10296480
    Abstract: A data processing system includes a central processing unit (CPU), a control block configured to interface with the CPU, a cache memory configured to interface with the control block and arranged to be spaced from the CPU by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the CPU by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells. The working memory is allocated to one memory layer selected among the plurality of memory layers. The storage memory is allocated to remaining memory layers among the plurality of memory layers.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Sung Cheoul Kim, Tae Ho Kim
  • Patent number: 10289569
    Abstract: An illegal address access blocking circuit includes a first register and a second register to set upper and lower limit values of an address range within which access to an external device is allowed. A first comparator compares a first value and the upper limit value, and outputs a high level signal when the first value is larger than the upper limit value. A second comparator compares the first value and the lower limit value, and outputs a low level signal. A first and logic circuit holds a logic sum of the high and low level signals, and outputs the logic sum as a third output, and a second logic circuit compares a fourth value inputted to a first request control line and the third output, and outputs a result of the comparison to a second request control line.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: May 14, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Yuki Kondoh
  • Patent number: 10289349
    Abstract: A local storage device (LSD) is provided configured to have a host device (HD) in communication with the LSD. The LSD includes a memory array. The LSD is configured to characterize data access usage of the LSD by at least one program executing on the HD. The LSD is configured to monitor access to the LSD as a result of data access operations by the HD relative to the memory array of the LSD. The LSD is additionally configured to determine characteristics of the monitored access. The LSD is additionally configured to, based on characteristics of the monitored access, determine and store data on the LSD indicative of the characterized monitored access.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: May 14, 2019
    Assignee: SanDisk IL, LTD.
    Inventors: Alain Nochimowski, Micha Rave, Itzhak Pomerantz, Eitan Mardiks
  • Patent number: 10268400
    Abstract: A non-volatile memory system may include a controller configured for parsing a host file system, identifying a location of a host file system directory and tracking directory entries of files deleted from the host file system directory but having valid data mappings in the logical-to-physical mapping table. The controller may then store the location of the host file system directory, monitor activity in the host file system directory and track validity status information for use in optimizing a compaction process. The compaction process may include segregating into separate compaction destination blocks valid data based on the stored validity status such that data valid in both the host file system directory and the logical-to-physical mapping table is in compaction destination blocks separate from data having valid logical-to-physical mapping entries but associated with deleted host file system directory entries.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: April 23, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Narendhiran Chinaaanangur Ravimohan, Muralitharan Jayaraman
  • Patent number: 10268598
    Abstract: A counter of a primary memory module provides a count indicative of the number of times the primary memory module has ever been read/written by a processor. With the count, an operating mode of the primary memory module is evaluated to optimize memory allocation performed by the data processing system, adjust the operating mode of the primary memory module, and send a warning message to a user, for example.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chang Li Ping, Alpus P. Chen, Chun-Wei Chen, Elysee Hsieh, Kelvin Shieh, Wei-Chin Tsai