Patents Examined by S. Jackson
  • Patent number: 5414584
    Abstract: The present invention discloses a gas venting system for use in metallic enclosures housing electrical circuit breakers of the type having gas vents in the circuit breaker case for venting gases produced during the interruption of a fault current. The enclosure includes one or more covers which provide access to the interior of the enclosure and one or more vents through which the circuit breaker gases can exit the enclosure. The gas venting system includes a gas chute made from an electrically nonconductive and substantially flame retardant material. The gas chute is generally tubular and hollow in shape and has a breaker end aperture and at lease one vent end aperture. The apertures communicate with one another through the hollow gas chute.
    Type: Grant
    Filed: June 9, 1993
    Date of Patent: May 9, 1995
    Assignee: Square D Company
    Inventor: Michael S. Young
  • Patent number: 5414587
    Abstract: A surge suppression device which fits over the end of an electrical plug and permits normal mating of the plug with the female receptacle. In the preferred embodiment, the device includes a body of metal-oxide varistor (MOV) material where one pin is connected to one plate on the MOV and another plug pin is connected to an opposing plate on the MOV. The MOV breaks down when experiencing excessive voltage levels to shunt potentially damaging voltages between the plug pins thereby preventing the spikes from reaching the protected equipment.
    Type: Grant
    Filed: December 30, 1992
    Date of Patent: May 9, 1995
    Assignee: TRW Inc.
    Inventors: Willie C. Kiser, Kevin G. Foreman, Paul J. Miller
  • Patent number: 5414586
    Abstract: A superconducting current limiting device for limiting overcurrent flowing in a load. The device includes a current limiter with a first superconducting coil, a second superconducting coil arranged coaxially with the first superconducting coil so as to have a negative magnetic coupling condition, and a third superconducting coil arranged coaxially with the first and second superconducting coils so as to have a negative magnetic coupling condition with the second superconducting coil and so as to have a positive magnetic coupling condition with the first superconducting coil. The first and second superconducting coils are electrically connected in series. The device includes a high speed switch connected electrically in series with the third superconducting coil to form a series circuit. The series circuit is electrically connected in parallel with the second superconducting coil.
    Type: Grant
    Filed: April 20, 1993
    Date of Patent: May 9, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsukushi Hara, Takeshi Ohkuma, Kazuyuki Tsurunaga, Daisuke Ito, Takamitsu Tada
  • Patent number: 5414583
    Abstract: A bus terminator, for a computer bus, which is capable of providing maximum allowable current to the bus, voltage clamping of the bus and steady state power reduction when the bus is in the positive steady state.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: May 9, 1995
    Assignee: Unitrode Corporation
    Inventor: Mark Jordan
  • Patent number: 5412528
    Abstract: A safety disconnect system for an installation comprising machines which are designed to interact, has a machine disconnect level in which a dedicated disconnect circuit is allocated to each machine, an area disconnect level, in which disconnect areas which comprise groups of associated machines can be disconnected, and a system disconnect level which is allocated to all the machines of the installation. The disconnect circuits in each case have an electrically operable switching element which is connected via safety circuits to a main box for the central control of the safety disconnect system and, through this box, to a power supply. The safety circuits have operable tripping elements at the area disconnect level and at the system disconnect level, are constructed as latching circuits and are passed through the main box in which they can optionally be linked to one another by means of a switching matrix such that groups of associated machines are disconnected if one of the tripping elements is operated.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: May 2, 1995
    Assignee: Ferag AG
    Inventors: Carl C. Mader, Giorgio Bovenzi, Robert Emmenegger
  • Patent number: 5412527
    Abstract: A circuit which protects against damage to an integrated circuit caused by electrostatic discharge (ESD) includes a resistor connected at one end to an input pad, and a pair of back-to-back Schottky diodes connected to the other end of the resistor. The cathodes of the Schottky diodes are connected to each other by a common semiconductor substrate and connected to a supply voltage. The anode of one of the Schottky diodes is grounded, and the anode of the other Schottky diode is connected to a node in common with the other end of the resistor and a circuit component to be protected from an ESD spike. The Schottky diodes, when forward biased by an ESD spike, do not inject minority carriers into the substrate. In this way, unwanted PNP, NPN, or four-layer diode problems are avoided and recovery from an ESD spike is rapid.
    Type: Grant
    Filed: June 2, 1993
    Date of Patent: May 2, 1995
    Assignee: Micrel, Incorporated
    Inventor: John D. Husher
  • Patent number: 5406438
    Abstract: An apparatus for triggering chemical augmented electrical fuses includes a light source which emits a light signal in the form of visible or infrared light energy upon receiving a signal from a control system, trigger signal source or other fuses. The light signal is coupled to a light detector by an optical coupling device such as a fiber optic cable. Upon receipt of the light signal, the light detector generates a signal which causes the application of electrical energy to exothermic material in a fuse, thereby detonating the material and causing interruption of current through the triggered fuse.
    Type: Grant
    Filed: May 24, 1994
    Date of Patent: April 11, 1995
    Assignee: General Electric Company
    Inventors: Radhakrishnan Ranjan, William E. Lazenby, Robert E. Koch, Gerald J. Carlson, John G. Leach, Ronald E. Bennet
  • Patent number: 5400203
    Abstract: An isolation circuit, which draws essentially zero current in a normal or stand-by state, uses a normally closed relay in combination with a storage element. A capacitor can be used as the storage element to energize the relay, using previously stored energy, in the event that a communication line to which the isolator is coupled exhibits a short circuit or low voltage condition. In this instance, the prestored energy on the capacitor activates the relay for a predetermined period of time, thereby open circuiting the communication line. When voltage is reapplied to one side of the isolator circuit, the relay is continuously energized and maintained in its open circuit condition until the low voltage or short circuit has been remedied.
    Type: Grant
    Filed: July 29, 1992
    Date of Patent: March 21, 1995
    Assignee: Pittway Corporation, a Delaware Corporation
    Inventor: Lee Tice
  • Patent number: 5400202
    Abstract: A circuit for protecting integrated circuits from electrostatic discharge by using SCR latchup to divert the ESD current pulse away from sensitive circuit structures. The SCR structure of the invention includes a trigger circuit having an NMOS triggering transistor for activating the SCR when an ESD event occurs on an input/output pad of the integrated circuit being protected. The ESD event on the input/output pad of the integrated circuit is detected by a circuit which applies a trigger voltage to the NMOS triggering transistor to initiate latchup of the SCR independent of junction breakdown of the NMOS triggering transistor. The trigger voltage is generated by an inverter trigger or a capacitor trigger powered by the ESD event so as to trigger SCR latchup so long as the integrated circuit is not powered up (V.sub.DD is low). The SCR of the invention may also have a floating well whereby the well resistor R.sub.
    Type: Grant
    Filed: June 15, 1992
    Date of Patent: March 21, 1995
    Assignee: Hewlett-Packard Company
    Inventors: Larry S. Metz, Gordon Motley, George Rieck
  • Patent number: 5398150
    Abstract: A protective device for electric loads coupled to power circuits, such as the ac power lines inside buildings, has a surge suppressor including a nonlinear surge-protective device in shunt with a resistor-capacitor damping network. This suppressor circuit is well coordinated with a suitable arrester connected to the power lines, for example at the point of entry of ac supply mains into the building. The arrester has a lower voltage protection level than the surge suppressor. This suppressor circuit limits transient voltages at the load and also damps the oscillatory surges that occur in a power connection as described.
    Type: Grant
    Filed: March 9, 1992
    Date of Patent: March 14, 1995
    Assignee: Dehn & Soehne GmbH
    Inventor: Ronald B. Standler
  • Patent number: 5392188
    Abstract: A power surge and transient voltage protection circuit includes a plurality of MOVs connected across power conductors leading to a load. The MOVs are in parallel with each other and in parallel with a selenium suppressor and with a capacitor. The selenium suppressor element has a minimum turn-on clamping voltage associated therewith that is below a voltage level that may cause damage to the load if such voltage were applied to the load. Each of MOVs has a minimum turn-on clamping voltage that is above that of the selenium suppressor, yet is still below that voltage level that could damage the load. The plurality of MOVs shunt a portion of a current across the supply conductors around the selenium suppressor as a rising voltage exceeds the selenium suppressor turn-on voltage.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: February 21, 1995
    Inventor: Barry M. Epstein
  • Patent number: 5392186
    Abstract: The electrical protection circuit disclosed comprises a latchup detection circuit, a threshold detector, an oscillator, a charge pump, a switching circuit, a voltage reference and detection circuit, and a signaling circuit. The latchup detection circuit, the threshold detector, the oscillator, the charge pump, and the switching circuit cooperate to provide latchup protection for the CMOS integrated circuit. The switching circuit provides integrated reverse current protection to the CMOS integrated circuit. The voltage reference and detection circuit, the threshold detector, and the signaling circuit provides low voltage protection for the SRAM-based software-downloaded Field Programmable Gate Array of the CMOS integrated circuit.
    Type: Grant
    Filed: October 19, 1992
    Date of Patent: February 21, 1995
    Assignee: Intel Corporation
    Inventors: James W. Alexander, Louis Johnson
  • Patent number: 5392185
    Abstract: In one form of the invention, an Electrostatic Discharge protection device containing at least one heterojunction transistor is disclosed. In another embodiment, an Electrostatic Discharge protection circuit comprises: a first terminal contact 20; an NPN heterojunction bipolar transistor Q2; a PNP bipolar transistor Q1; a base-emitter shunt resistor R2; an emitter of said PNP transistor connected to said first terminal contact; a base of said PNP transistor connected to collector of said NPN transistor; a collector of said PNP transistor connected to a base of said NPN transistor; and an emitter of said NPN transistor connected to a second terminal contact 22, with said base-emitter shunt resistor connected between said base of said NPN transistor and an emitter of said NPN transistor, whereby a low-capacitance device capable of protecting semiconductor devices from electrostatic discharges in excess of 4000 Volts results. Other devices, systems, and methods are also disclosed.
    Type: Grant
    Filed: May 29, 1992
    Date of Patent: February 21, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Glen R. Haas, Jr., Thomas E. Nagle
  • Patent number: 5390069
    Abstract: A current limit circuit is provided, with a DMOS output transistor DM2. A second DMOS transistor DM1 is provided in parallel with DM2. A pair of matched resistors R12 and R13 are connected to a reference current source and to DM1. If the voltage across R13 exceeds the voltage across R12, a control circuit sinks current away from DM1.
    Type: Grant
    Filed: September 24, 1993
    Date of Patent: February 14, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Andrew Marshall
  • Patent number: 5386336
    Abstract: A current limiting circuit and technique is provided for preventing excessive current supplied to a circuit and for providing self-recovery characteristics thereto. The current limiting circuit includes an input for receiving a supply voltage for supplying power to the monitored circuit and an output for providing the power to the desired circuit being monitored. The circuit employs a drive transistor having a source connected to the input and a drain connected to the output. The drive transistor further includes a gate for receiving a control signal. A current mirror circuit is provided for sensing a current overload and adjusting the control signal to indicate the amount of current drawn. During normal current draw, the circuit provides the supply voltage as the output. When excessive current draw is detected, the drive transistor is turned off and the output current is thereby cut off. When the current decreases to normal current loads, the drive transistor is turned back on.
    Type: Grant
    Filed: June 19, 1992
    Date of Patent: January 31, 1995
    Assignee: TRW Inc.
    Inventors: Jason S.-M. Kim, James M. Anderson
  • Patent number: 5384678
    Abstract: Control and self-monitoring system for an electrical apparatus comprising three poles, each including a closing coil and an opening coil, an opened auxiliary contact, and a closed auxiliary contact, wherein each of the poles is provided with a microprocessor receiving, in particular, information from the opened auxiliary contacts and controlling two static relays in series respectively with the circuit of the opening coil and in the circuit of the closing coil, the microprocessors being subscribers to a local bus comprising a serial bus under the control of a management member and connected to a processor station receiving the signals collected by the microprocessors and the signals issued by the protection devices or by the operator.
    Type: Grant
    Filed: June 8, 1993
    Date of Patent: January 24, 1995
    Assignee: Gec Alsthom T & D SA
    Inventors: Gerard Ebersohl, Edmond Thuries
  • Patent number: 5383082
    Abstract: A circuit for providing an overcurrent protection for a power element, such as an IGBT, MOSFET or bipolar transistor, which is inserted between the power supply and a load, the protection circuit comprising a control circuit that provides an input to a gate amplifier at the power element gate. The gate amplifier comprises a photodiode that is connected between the amplifier power supply and the power element gate. The photodiode provides a clamp of the gate voltage in the event of an overcurrent and communicates optically with a phototransistor to provide a detection signal that can modify the control circuit operation. Specifically, the detection circuit can modify the input to the control circuit or control the output of the control circuit so that the energization of the power element is stopped or limited. The control can be through Darlington-connected transistors at the output of the phototransistor.
    Type: Grant
    Filed: May 15, 1992
    Date of Patent: January 17, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yuji Nishizawa
  • Patent number: 5383080
    Abstract: A voltage limiter circuit is disposed in a semiconductor IC chip in order to reduce an operating voltage of an internal circuit of a scaled-down element. A small capacitance of a Vcc wiring by the disposition constitutes a resonance circuit together with an inductance of the Vcc wiring. Resonance at the resonance circuit causes large variation of a supply current and noise. An additional capacitance is connected between the Vcc wiring and a Vss wiring in order to suppress the variation and noise. The capacitance is formed by a PN junction and is connected in series to a damping resistance.
    Type: Grant
    Filed: July 24, 1992
    Date of Patent: January 17, 1995
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corporation
    Inventors: Jun Etoh, Masakazu Aoki, Masashi Horiguchi, Shigeki Ueda, Hitoshi Tanaka, Kazuhiko Kajigaya, Tsugio Takahashi, Hiroshi Kawamoto
  • Patent number: 5383083
    Abstract: A protective apparatus for a power transistor which detects an abnormal temperature of a power transistor and cuts a load to the power transistor to prevent possible breakdown of the power transistor. The protective apparatus comprises detecting means which detects a junction temperature of the power transistor on the real time basis from a base-emitter voltage of the power transistor. When the junction temperature of the power transistor is excessively high, a protective circuit produces an output signal, and a muting circuit applies muting to an input signal to or a current flow through the power transistor.
    Type: Grant
    Filed: June 29, 1992
    Date of Patent: January 17, 1995
    Assignee: Pioneer Electronic Corporation
    Inventors: Ryuichi Shinoda, Jun Honda, Kunihiro Miyata
  • Patent number: 5381295
    Abstract: A battery drain limitation circuit, for use in engine-powered vehicles and equipment that rely on a battery for starting the engine and for operating accessories, disconnects the battery from all loads when the battery voltage falls to a level below which the battery charge may be insufficient to start the engine. The circuit is rendered inoperable, when the engine is running, by means of a microphone that detects engine noise. The circuit includes a reset mechanism that reconnects the battery to all loads. The reset mechanism may be automatic or manually actuated. A timing circuit delays the disconnection for a period of time sufficient to start the engine. The drain limitation circuit employs a latching relay that, in its preferred embodiment, includes front and rear coils in tandem, axially separated by a collar with an internal detent. A front plunger and a rear plunger are disposed for axial movement within the coils and the collar.
    Type: Grant
    Filed: July 14, 1992
    Date of Patent: January 10, 1995
    Assignee: Datamax Electronics, Inc.
    Inventors: Larry Rund, Richard P. Hewitt, Stuart Sigafoos