Patents Examined by S. Jackson
  • Patent number: 5379177
    Abstract: A transient voltage surge suppressor comprises a first series circuit formed of a normally-off voltage surge-responsive gas discharge tube and a first voltage clamping device connected across input terminals to which a line voltage is applied. It also includes a second series circuit formed of a first electrical energy absorbing impedance element and a second voltage clamping device connected across the first voltage clamping element, thereby forming a voltage-clamping, voltage divider circuit which clamps the voltage across the first voltage clamping element at a voltage level reduced in comparison with that obtained by the first series circuit alone. When the gas discharge tube turns on, it places both voltage clamping devices in the circuit simultaneously, so that the let-through voltage appearing across output terminals can be reduced to the voltage clamped by the voltage-clamping, voltage divider circuit.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: January 3, 1995
    Assignee: Atlantic Scientific
    Inventor: Anthony O. Bird
  • Patent number: 5379174
    Abstract: In a semiconductor integrated circuit device including a substrate bias voltage generating circuit supplying a substrate bias voltage to internal circuit performing original functions and a substrate where the internal circuit is formed, an N channel MOS transistor is provided between the internal circuit and power supply pad receiving an external voltage Vcc for driving the circuit. The transistor is controlled such that it is rendered conductive when substrate potential V.sub.SB is higher than the threshold voltage of MOS transistor and non-conductive when potential V.sub.SB is lower than the threshold voltage. Since supply of power supply voltage Vcc to the internal circuit is interrupted if latch-up is caused in the internal circuit and substrate potential V.sub.SB rises, internal circuit is immediately freed from the latch-up state even if latch-up is caused. Therefore, the internal circuit is protected from being heated or destructed by a current due to the latch-up.
    Type: Grant
    Filed: July 13, 1992
    Date of Patent: January 3, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masayuki Kasamoto
  • Patent number: 5373412
    Abstract: The communication circuit of the self-powered trip device is disabled by the trip device microprocessor when the values of the measured currents are lower than preset values. The microprocessor sends a bit, called the power saving bit, before disabling the communication circuit so as to inform a monitoring device connected to the trip device of the cause of the interruption of transmission from the trip device.
    Type: Grant
    Filed: September 15, 1992
    Date of Patent: December 13, 1994
    Assignee: Merlin Gerin
    Inventor: Gilles Dousse
  • Patent number: 5369541
    Abstract: There is disclosed a monitoring apparatus for a multiphase electrical system of very simple and reliable circuit design capable of monitoring such a system and producing fault signals to operate protective relays and for visual indication. A main component of the apparatus is a multiphase, full-wave bridge rectifier circuit having matched voltage dropping input resistors so that the output of the bridge is a low voltage fluctuating DC signal such that neither the semiconductor diode rectifiers of the full-wave bridge or other internal components of the monitoring apparatus are exposed to high power line voltages. Phase unbalance in the apparatus is detected by evaluating the ratio of the peak to trough voltage of the fluctuating DC signal produced by the full-wave bridge.
    Type: Grant
    Filed: August 13, 1992
    Date of Patent: November 29, 1994
    Assignee: Diversified Electronics, Inc.
    Inventor: Henno Normet
  • Patent number: 5365398
    Abstract: Disclosed is a lightning attractor apparatus for protecting secondary structures within the lightning protection zone of said lightning attractor apparatus, which is electrically grounded to the body of earth and ground water having reference potential. The apparatus includes a central conductive rod, one or more coaxial cylindrical conductors of decreasing height with the lowest cylindrical conductor on the outside, and a conducting base means onto which all above-ground conductors are rigidly mounted, and which provides the link with a common grounding rod. The grounding rod provides the electrical connection of the apparatus with the reference ground potential. Insulative concentric spacers, located at more or less regular intervals along the axis, separate and isolate the above-ground conductors from one another, their separation being such that arc-over between adjacent conductors are effectively suppressed.
    Type: Grant
    Filed: July 24, 1992
    Date of Patent: November 15, 1994
    Inventor: Richard Briet
  • Patent number: 5357392
    Abstract: Disclosed is a motor drive device with tacho-generator that can be configured as a back-up motor. This device is designed for the driving of a movable element. It comprises an electrical rotor motor with supply coil, associated with a tachometrical sensor inducing an electrical current in at least one electrical coil, a regulator circuit controlling the speed and the position of the electrical motor as a function of the servo signal delivered by said electrical coil and applied to the supply coil. This device further comprises means to continue the driving of the movable element in the event of the malfunctioning of the electrical motor or of its electrical supply. These means to continue the driving of the movable element are constituted by a failure detection circuit which, in the event of failure, activates switching means to connect the electrical coil of the tachometrical sensor to an electrical supply source. Application: improvement of the safety of a motor drive mechanism.
    Type: Grant
    Filed: July 9, 1992
    Date of Patent: October 18, 1994
    Assignee: Thomson-CSF
    Inventors: Patrick Guyomard, Marc Audion, Jean Rambeaud, Philippe Riviere
  • Patent number: 5357393
    Abstract: An integrated high voltage device with an ultra low leakage input protection circuit to be used in highly sensitive circuits which require ultra low input leakage current. The protection circuit has a common substrate with the integrated circuit device and the common substrate is floating. The floating substrate provides a way of designing a protection circuit with small diodes which have ultra low input D.C. leakage. The protection circuit includes a resistor and two small Zener diodes which can clamp and protect the device during normal operating conditions up to voltages such as 1700 volts.
    Type: Grant
    Filed: May 5, 1992
    Date of Patent: October 18, 1994
    Assignee: Xerox Corporation
    Inventors: Mohamad M. Mojaradi, Guillermo Lao, Dale Sumida
  • Patent number: 5357395
    Abstract: An undervoltage protection circuit, system and method is prodded for sending a reset signal to an electronic device during undervoltage time periods in which the device power supply voltage is less than a desired amount. The protection circuit includes a sensing circuit and a latching network adapted to quickly discharge a storage capacitor when the sensing circuit senses the undervoltages. A buffer network is included to send a reset signal to the electronic device whenever the storage capacitor discharges to a low latched level. The reset signal exists substantially throughout the undervoltage time period and also for a set delay period after the undervoltage time period ceases. During receipt of the reset signal, the electronic device will be inhibited from incurring damage or loss of data.
    Type: Grant
    Filed: June 25, 1992
    Date of Patent: October 18, 1994
    Assignee: Schlumberger Technology Corporation
    Inventors: Steven A. Bissell, Robert B. Hyde, Marvin W. Rasmussen
  • Patent number: 5355274
    Abstract: A fused disconnect device constructed according to the present invention comprises a housing, a line side terminal, a load side terminal, a protection fuse holder assembly removably installed in a cavity of said housing, and a separate alarm fuse removably installed in said housing. The alarm fuse may remain installed in the housing regardless of the presence of the protection fuse holder assembly, so that an alarm will be generated whenever the inventive device has interrupted power to the load. In a first embodiment of the invention, the disconnect device is adapted for front-access mounting in a power distribution panel. In a second embodiment of the invention, the disconnect device is adapted for rear-access mounting in a power distribution panel. A third embodiment is adapted for use in higher-current applications.
    Type: Grant
    Filed: November 5, 1991
    Date of Patent: October 11, 1994
    Assignee: Cooper Industries, Inc.
    Inventors: David R. Marach, Conrad Alfaro, Lawrence Happ
  • Patent number: 5353189
    Abstract: A surge protection device for low level electronic systems and especially conventional roadway traffic monitoring equipment connected to embedded roadway sensors, which includes, for each sensor, first and second stage common mode and normal mode surge arrestor circuits and which stages are connected by a common mode choke in series with the sensor circuit and monitoring equipment. The first and second stage surge arrestor circuits and choke are preferably mounted on surge arrestor circuit boards having enlarged conductive traces and peripheral ground contact surfaces which enable large surge currents to pass to ground when the boards are mounted to a common grounding backplane.
    Type: Grant
    Filed: November 2, 1992
    Date of Patent: October 4, 1994
    Inventor: John C. Tomlinson
  • Patent number: 5353188
    Abstract: An overcurrent detector circuit for a circuit-breaker includes two systems for overcurrent detection. In the first system, the level of the current detected by the current detectors 41 is converted to a digital signal by the A/D converter 91 at each 500 microseconds. The maximum value detector 92 selects the maximum value among these digital signals over each period of 12.5 milliseconds. When the maximum value is greater than a pick-up level, the square thereof is accumulated in the counter 95. In the second system, the calculation circuit 96 squares the digital signals of the A/D converter 91, and switches its outputs in order to the counters 97-1 through 97-5 at a period of 25 milliseconds. Thus, the four counters other than that currently coupled to the calculation circuit 96 hold together the squares of the digital signals accumulated over 100 milliseconds.
    Type: Grant
    Filed: March 3, 1993
    Date of Patent: October 4, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshihiro Hatakeyama
  • Patent number: 5349489
    Abstract: An integrated semiconductor circuit for use in a low voltage (1.5-2 V) battery operated device is provided with a protection circuit against reverse connection of the battery.The protection circuit takes care that the substrate is always connected to one extreme potential and a region containing one or more resistors is always connected to the other extreme potential irrespective of the proper or reverse mode of connection of the battery. The protection circuit has been designed in such a way that no voltage drop occurs between the battery connections and the supply voltage connection terminals of the integrated semiconductor circuit.
    Type: Grant
    Filed: December 12, 1991
    Date of Patent: September 20, 1994
    Assignee: B.V. Optische Industrie "De Oude Delft"
    Inventor: Johannes B. J. Schelen
  • Patent number: 5345356
    Abstract: A particular electrostatic discharge (ESD) protection problem is faced when only n-channel output transistors are present, since there is no p-n junction that could serve to clamp positive ESD voltages, as would be the case if a p-channel output transistor were present. In the present technique, the output transistor itself is used to conduct the ESD current to a power supply conductor (V.sub.SS). To assist in the turn-on of the n-channel output transistor, a transistor couples the bond pad to the n-tub in which the p-channel pre-driver transistor is formed. Conduction through this transistor raises the n-tub voltage when an ESD event occurs, thereby preventing the p-n junction of the p-channel pre-driver transistor from clamping the turn-on voltage, which would limit the protection obtained by this technique. This technique is especially valuable for SCSI (Small Computer System Interface) chips, since only n-channel output transistors are used.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: September 6, 1994
    Assignee: AT&T Bell Laboratories
    Inventor: Juergen Pianka
  • Patent number: 5343350
    Abstract: A circuit configuration for protecting the on-board electrical system of a motor vehicle includes an input connected to a voltage source, an output connected to a load and a ground connection being common to both the input and the output. A current stabilizer regulates an output current. A switch controls the current stabilizer as a function of the output current. An overload switch carries an overload current from the input through the current limiter to the output upon the appearance of an overload at the output, and carries a short-circuit current from the output through the excess voltage switch to ground upon a short circuit at the output to an excess voltage.
    Type: Grant
    Filed: March 30, 1992
    Date of Patent: August 30, 1994
    Assignee: Siemens Aktiengesellschaft
    Inventors: Klaus Pohl, Alfons Fisch
  • Patent number: 5341268
    Abstract: A main controller installed in a distribution substation of an electric power system sends a request signal to each of section controllers installed in individual section switches upon detecting a distribution line fault. Each of the section controllers performs fault detection individually. Each section controller judges whether its associated section switch is dividing the distribution line between faulty and normal line sections on the basis of fault detect signals from the other section controllers. If it is judged that its associated section switch is dividing the distribution line between faulty and normal line sections, that section controller opens its associated section switch.
    Type: Grant
    Filed: December 14, 1992
    Date of Patent: August 23, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Ishiguro, Kazutoyo Narita, Masahide Susuta
  • Patent number: 5337208
    Abstract: An AC current limiter, which is connected in series with a transmission line and which operates in two modes, a conductive mode and a protective mode, includes first and second transistors coupled in parallel with first and second diodes, respectively and the emitters of the first and second transistors serially coupled by a sensing element. First and second gain control networks are couple to the first and second transistors, respectively, to permit control of the gain in the first and second transistors. More particularly, as line current increases to a limiting value, the circuit operates in the protective mode. The voltage across the sensing causes a transistor in one of the first and second networks to turn on, thus diverting current from the respective first and second transistors connected in series with the transmission line. Therefore, line current is limited to a predetermined value.
    Type: Grant
    Filed: December 18, 1991
    Date of Patent: August 9, 1994
    Assignee: NEC America, Inc.
    Inventor: Steven E. Hossner
  • Patent number: 5335132
    Abstract: First and second resistors are connected in series with a Zener diode between first and second points of operating potential. The base-to-emitter of an NPN transistor is connected across the first resistor to sense the current through the series path. The collector-to-emitter of a PNP transistor is connected across the second transistor, whereby when the PNP transistor is turned-on hard and into saturation, the voltage drop across the second transistor decreases. The collector of the NPN transistor is connected to the base of the PNP transistor, whereby when an overvoltage condition exists and the Zener diode breaks down, the two transistors are driven regeneratively and form a latch and the operating point of the circuit is shifted.
    Type: Grant
    Filed: June 17, 1991
    Date of Patent: August 2, 1994
    Assignee: Harris Corporation
    Inventor: Thomas R. DeShazo, Jr.
  • Patent number: 5335135
    Abstract: A low voltage electric power monitoring and circuit breaker system includes two processors. The first processor activates the circuit breaker when an overcurrent condition is detected and the second processor monitors the current sensed by the first processor and logs overcurrent values which arm the breaker as well as overcurrent values existing at the time the breaker is tripped.
    Type: Grant
    Filed: June 8, 1993
    Date of Patent: August 2, 1994
    Assignee: Siemens Energy & Automation, Inc.
    Inventor: Michael A. Kinney
  • Patent number: 5333094
    Abstract: A transient reduction circuit is provided for use in an arrangement including a backplane having at least two conductors, a power supply connected to the conductors, and a plurality of circuit cards attached to the backplane and connected to the conductors. Each of the plurality of circuit cards includes a transient reduction circuit having inputs for connection to the power supply output and a reference potential, a transistor having an emitter connected to the power input, a collector connected to the load and a base, a resistor connected between the base and the reference potential input, and a decoupling capacitor connected between the collector and the reference potential input. When the cards are powered the transistor is turned on and saturates, thus introducing only a 0.1 V drop in the power supply line. A sudden decrease in power supply voltage output is prevented from discharging the decoupling capacitor by a reverse biased base-collector junction in the transistor.
    Type: Grant
    Filed: June 17, 1992
    Date of Patent: July 26, 1994
    Assignee: Northern Telecom Limited
    Inventor: Dermot T. Fucito
  • Patent number: 5333087
    Abstract: A superconducting magnet apparatus has two or more divided superconducting coils successively arrayed in series and a magnetic shield. The divided superconducting coils arrayed in the axial direction are successively electrically connected in series, and protective diodes are connected between two connection points symmetrically-located with respect to the center of the serially-connected superconducting coil array as a reference.
    Type: Grant
    Filed: June 23, 1993
    Date of Patent: July 26, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Moriaki Takechi, Tatsuya Oue