Abstract: It is to provide a manufacturing method of a semiconductor device including the following step of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 ?g/m3 and less.

Abstract: A method of forming an interconnect with a bamboo grain microstructure. The method includes forming a conductive filler layer in a trench of an insulating layer to a predetermined depth such that an aspect ratio of a top portion of the trench is reduced to a threshold level, depositing a metal layer over the conductive filler layer in the top portion of the trench, the metal layer having a plurality of small grains, and annealing the metal layer to provide a bamboo grain microstructure having larger grains than grain boundaries of the plurality of small grains.

Abstract: A method of forming an interconnect with a bamboo grain microstructure. The method includes forming a conductive filler layer in a trench of an insulating layer to a predetermined depth such that an aspect ratio of a top portion of the trench is reduced to a threshold level, depositing a metal layer over the conductive filler layer in the top potion of the trench, the metal layer having a plurality of small grains, and annealing the metal layer to provide a bamboo grain microstructure having larger grains than grain boundaries of the plurality of small grains.

Abstract: A structure and method for fabricating a semiconductor device is described. A device structure including a gate structure, a source region and a drain region is disposed on a first surface of a substrate. Contact holes are etched through the source and drain regions and through a first portion of the substrate. The contact holes are filled with a conductive material to produce contact studs coupled to the source and drain regions. A second portion of the substrate is removed. A surface of the contact studs is exposed through a second surface of the substrate opposite to the gate structure for connection to a wiring layer disposed over the second surface of the substrate.

Abstract: A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.

Abstract: According to one embodiment, the first separation film separates the control electrode, the first insulating layer, the charge storage layer, the intermediate insulating layer, the floating electrode layer, and the second insulating layer in a first direction. The second separation film separates a first stacked unit in a second direction. The first stacked unit includes the charge storage layer, the intermediate insulating layer, the floating electrode layer, the second insulating layer, and the semiconductor layer. The second direction intersects the first direction. The second separation film contains silicon.

Abstract: A method for densifying a dielectric film on a substrate includes arranging a substrate including a dielectric film on a substrate support in a substrate processing chamber; supplying a gas mixture including helium and oxygen to the substrate processing chamber; controlling pressure in the substrate processing chamber to a pressure greater than or equal to a predetermined pressure; supplying a first power level at a first frequency to a coil to create plasma in the substrate processing chamber. The coil is arranged around an outer surface of the substrate processing chamber. The method includes densifying the dielectric film for a predetermined period. The pressure and the first power level are selected to prevent sputtering of the dielectric film during densification of the dielectric film.

Abstract: The present invention provides an array substrate fabricating method. The array substrate fabricating method comprises the steps of: forming a semiconductor material layer and a first photoresist layer on a substrate successively, forming a pattern of an active layer comprising thin film transistors by using the semiconductor material layer and the first photoresist layer through photoetching technology, and reserving the first photoresist layer at least on conductive areas of the active layer when the thin film transistors are turned on; and forming a first material layer on the substrate on which the active layer is formed and the first photoresist layer is reserved on the active layer, and forming a pattern comprising first structures by using the first material layer through the photoetching technology. The method is adapted for fabricating an array substrate using metal oxide thin film transistors.

Abstract: A a chip and a method for producing the chip with a plurality of measurement regions which are provided with electrodes for electrically detecting reactions in which, in order to reliably separate the individual measurement regions from one another, a monolayer of a fluorosilane is formed on the chip surface which has strongly hydrophobic properties. Therefore, during spotting with a liquid, the drops of liquid applied by spotting can be reliably prevented from coalescing, and thus, causing mixing of the substances in the drops of liquid which are supposed to be immobilized in the measurement regions.

Abstract: Embodiments of the present disclosure describe an integrated circuit and associated fabrication techniques and configurations, which may include forming on at least one of a metal layer or a polymer layer of an integrated circuit die a surface layer that includes an adhesion-functional group, and applying to the surface layer a next layer to adhere to the surface layer with the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a polymer layer, forming the surface layer may include copolymerizing on the polymer layer a polar monomer that includes the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a metal layer, forming the surface layer may include forming on the metal layer a self-assembled monolayer that includes amine group terminations. Other embodiments may be described and/or claimed.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate and a laminated body. The laminated body is disposed on the semiconductor substrate. The laminated body includes a plurality of conducting layers and a first interlayer insulating film. The first interlayer insulating film is disposed between the plurality of conducting layers. A second interlayer insulating film is formed to cover this laminated body. The second interlayer insulating film includes boron.

Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a source/drain feature over a substrate, forming a dielectric layer over the source/drain feature, forming a contact trench through the dielectric layer to expose the source/drain feature, depositing a titanium nitride (TiN) layer by a first atomic layer deposition (ALD) process in the contact trench and depositing a cobalt layer over the TiN layer in the contact trench.

Abstract: A high-voltage flip LED chip and a manufacturing method thereof. In the high-voltage flip LED chip, a P-N electrode connecting metal block is filled into an isolation trench between two adjacent chip units and is respectively filled into a first electrode hole of one chip unit and a second electrode hole of the other chip unit to serially connect the two adjacent chips.

Abstract: This work provides a new approach for epitaxial liftoff. Instead of using a sacrificial layer that is selectively etched chemically, the sacrificial layer selectively absorbs light that is not absorbed by other parts of the structure. Under sufficiently intense illumination with such light, the sacrificial layer is mechanically weakened, melted and/or destroyed, thereby enabling epitaxial liftoff. The perimeter of the semiconductor region to be released is defined (partially or completely) by lateral patterning, and the part to be released is also adhered to a support member prior to laser irradiation. The end result is a semiconductor region removed from its substrate and adhered to the support member.

Abstract: A method of fabricating a semiconductor device is provided as follows. A source/drain pattern is formed on a substrate. The source/drain pattern contains silicon atoms and germanium atoms. At least one germanium atom is removed from the germanium atoms of the source/drain pattern.

Abstract: A high voltage LED flip chip includes two or more regions; a Mesa-platform, the Mesa-platform in each region has a first groove; a first electrode located on the Mesa-platform, an area between the first electrodes in two adjacent regions forms a second groove; a first insulation layer covering the Mesa-platforms and the first electrodes, the first insulation layer fills the second groove and partially fills the first groove, and a part of the first groove which is not filled forms a third groove; a fourth groove formed in the first insulation layer, the fourth groove exposes a surface of the first electrode; and an interconnection electrode, the interconnection electrode comprises a first portion connecting the first semiconductor layer through the third groove in a particular region with the first electrode through the fourth groove in another region adjacent to the particular region. The LED formed has improved performance.

Abstract: An apparatus for and a method of forming a plurality of groups of laser beams (2, 2?, 2?) are defined. Each group (2, 2?, 2?) may comprise two or more laser beams. The apparatus comprises a first diffractive optical element (3, referred as DOE) and a second diffractive optical element (8), the first DOE (3) being arranged to receive a first laser beam (1) and to divide this into a plurality of second laser sub-beams and the second DOE (8) being arranged to receive said plurality of second laser sub-beams and to divide each of these into two or more groups of third laser sub-beams (2, 2?, 2?), the separation of the groups in a direction perpendicular to a first axis being adjustable by rotation of the first DOE (3) about its optical axis and the separation of the third laser sub-beams (2, 2?, 2?) within each group in a direction perpendicular to the first axis being adjustable by rotation of the second DOE (8) about its optical axis.

Abstract: A semiconductor device includes a diode region and an IGBT region. The diode region includes a front side anode region, an n-type diode barrier region, an n-type diode pillar region reaching the diode barrier region through the front side anode region, and a p-type back side anode region separated from the front side anode region by the diode barrier region. The IGBT region includes a front side body region, an n-type IGBT barrier region, and a back side body region separated from the front side body region by the IGBT barrier region. When a gate-off voltage is applied to a gate electrode, a resistance between the IGBT barrier region and the emitter electrode is higher than a resistance between the diode barrier region and the anode electrode.

Abstract: A light-emitting diode chip package and a manufacturing process thereof sequentially includes a transparent layer, a fluorescent layer, a wafer layer, a light-emitting diode chip, a dielectric layer, a metal circuit layer, and a protective film and conductive blocks used to draw out the electrodes of the light-emitting diode chip. The outer surfaces of the fluorescent layer and the wafer layer retreat from the fluorescent layer down to the wafer layer to form a slant, and the dielectric layer, the metal circuit layer, and the protective film spread out to coat the slant. Simple techniques at low cost are involved.