Patents Examined by S. M. S Imtiaz
  • Patent number: 9620628
    Abstract: A method to fabricate a semiconductor device includes forming a semiconductor fin on a substrate; forming a dummy gate material layer over the semiconductor fin; forming a contact hole in the dummy gate material layer; forming a source/drain feature in the contact hole; forming a contact feature on the source/drain feature within the contact hole; and replacing a dummy gate that is formed of the dummy gate material layer with a metal gate.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gin-Chen Huang, Hui-Chi Huang, Yung-Cheng Lu
  • Patent number: 9620360
    Abstract: A method comprises providing a cavity structure on the substrate comprising a first growth channel extending in a first direction, a second growth channel extending in a second direction, wherein the second direction is different from the first direction and the second channel is connected to the first channel at a channel junction, a first seed surface in the first channel, at least one opening for supplying precursor materials to the cavity structure, selectively growing from the first seed surface a first semiconductor structure substantially only in the first direction and in the first channel, thereby forming a second seed surface for a second semiconductor structure at the channel junction, growing in the second channel the second semiconductor structure in the second direction from the second seed surface, thereby forming the semiconductor junction comprising the first and the second semiconductor structure.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mattias B. Borg, Kirsten E. Moselund, Heike E. Riel, Heinz Schmid
  • Patent number: 9601570
    Abstract: A structure of a semiconductor device is described. A device structure including a gate structure, a source region and a drain region is disposed on a first surface of a substrate. Contact holes are etched through the source and drain regions and through a first portion of the substrate. The contact holes are filled with a conductive material to produce contact studs coupled to the source and drain regions. A second portion of the substrate is removed. A surface of the contact studs is exposed through a second surface of the substrate opposite to the gate structure for connection to a wiring layer disposed over the second surface of the substrate.
    Type: Grant
    Filed: July 31, 2016
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Carl J Radens, Richard Q Williams
  • Patent number: 9595565
    Abstract: The present invention relates to a memory structure, which is a kind of resistive memory. A middle layer formed by a first dielectric film and a second dielectric film is included between the top and bottom electrodes. The material of the top electrode is iridium oxide. Thereby, preferred oxygen vacancy filament paths can be provided and thus exhibiting complementary resistive switching of memory arrays. Furthermore, the memory structure can be applied to biological tests.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: March 14, 2017
    Assignee: Chang Gung University
    Inventors: Siddheswar Maikap, Subhranu Samanta
  • Patent number: 9589843
    Abstract: The manufacturing efficiency of a semiconductor device is improved. A method for manufacturing a semiconductor device includes a step of sealing a semiconductor chip using a mold die having a cavity, a gate part communicating with the cavity, and a vent part provided opposite to the gate part via the cavity, and extending in a first direction in a sealing step. Further, a lead frame has a first through hole provided at a position overlapping the cavity in the sealing step, and a second through hole provided outside the first through hole, and provided at a position overlapping the vent part in the sealing step. Whereas, in a second direction crossing with the first direction, the length of the second through hole is larger than the length (groove width) of the vent part.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: March 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Junji Ikura
  • Patent number: 9589846
    Abstract: A method for forming a semiconductor device is provided. First, a dielectric layer is provided on a substrate, wherein a first recess and a second recess are formed in the dielectric layer. After a mask layer is filled into the first recess and the second recess, the mask layer in the second recess is removed away, thereby forming a patterned mask layer. Subsequently, a nitride treatment is performed to remove unwanted residue of the mask layer in the second recess.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: March 7, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Yu Tsai, Wei-Hsin Liu, Han-Sheng Huang
  • Patent number: 9590139
    Abstract: A light emitting module including a driving unit and a light emitting diode is provided. The light emitting diode is electrically connected to the driving unit and the driving unit provides an operating current to make the light emitting diode emit light. The light emitting diode includes an n-type semiconductor layer, a light-emitting layer, an electron-blocking layer, and a p-type semiconductor layer. The electron-blocking layer has a thickness, and the thickness is smaller than or equal to 30 nm or is larger than or equal to 80 nm. The light-emitting layer is located between the electron-blocking layer and the n-type semiconductor layer. The electron-blocking layer is located between the p-type semiconductor layer and the light-emitting layer. A ratio of current density of the light emitting diode to the thickness is larger than 0 and is smaller than or equal to 2.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: March 7, 2017
    Assignee: PlayNitride Inc.
    Inventors: Yen-Lin Lai, Jyun-De Wu
  • Patent number: 9583346
    Abstract: A method for manufacturing a silicon carbide semiconductor device includes steps below. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface having a maximal diameter greater than 100 mm, is prepared. An impurity region is formed on a side of the first main surface of the silicon carbide substrate. In a plan view, a cover member is arranged on the side of the first main surface so as to cover at least the entire impurity region. The silicon carbide substrate is annealed at a temperature lower than a melting point of the cover member while the cover member is arranged on the side of the first main surface of the silicon carbide substrate.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: February 28, 2017
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shunsuke Yamada, Takeyoshi Masuda, Taku Horii
  • Patent number: 9559240
    Abstract: In one example, a device includes a trench formed in a substrate. The trench includes a first end and a second end that are non-collinear. A first plurality of semiconductor pillars is positioned near the first end of the trench and includes integrated light sources. A second plurality of semiconductor pillars is positioned near the second end of the trench and includes integrated photodetectors.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Yann Astier, Huan Hu, Ning Li, Devendra K. Sadana, Joshua T. Smith, William T. Spratt
  • Patent number: 9548354
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a first conductivity type. An epitaxial layer having the first conductivity type is disposed on the substrate, and a trench is formed in the epitaxial layer. A polysilicon layer having the first conductivity type fills the trench, and a first doping region having a second conductivity type that is different from the first conductivity type is disposed in the epitaxial layer and on sidewalls of the trench. A method for forming the semiconductor device is also provided.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: January 17, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chia-Hao Lee, Po-Heng Lin, Chih-Cherng Liao, Jun-Wei Chen