Abstract: Various embodiments may relate to a method for producing an optoelectronic component, including forming a first electrode on a substrate, arranging a first mask structure on or above the substrate, wherein the first mask structure comprises a first structuring region including an opening and/or a region prepared for forming an opening, arranging a second mask structure on or above the first mask structure, forming a second structuring region in the first mask structure and in the second mask structure in such a way that at least one part of the first structuring region in the first mask structure is formed outside the second structuring region in the first mask structure.

Abstract: A nitride semiconductor light emitting device includes a substrate as a base and an n-type semiconductor layer grown on a surface side of the substrate. Antimony (Sb) is added to the n-type semiconductor layer so that a molar fraction is not less than 0.1% and is less than 1%. A concentration of an n-type impurity in the n-type semiconductor layer is lower than an electron concentration.

Abstract: A method of manufacturing a switching element is provided. The method includes forming a pillar-shaped structure having a first electrode, an insulation layer and a second electrode which are stacked on a substrate. A tilted doping process is performed to inject dopants into at least a portion of the insulation layer. The tilted doping process forms a threshold switching operation region in the insulation layer.

Abstract: A pattern wafer (10) for LEDs is provided with an uneven structure A (20) having an arrangement with n-fold symmetry substantially on at least a part of the main surface, where in at least a part of the uneven structure A (20), a rotation shift angle ? meets 0°<??(180/n)° in which ? is the rotation shift angle of an arrangement axis A of the uneven structure A (20) with respect to a crystal axis direction in the main surface, and a top of the convex-portion of the uneven structure A (20) is a corner portion with a radius of curvature exceeding “0”. A first semiconductor layer (30), light emitting semiconductor layer (40) and second semiconductor layer (50) are layered on the uneven structure A (20) to constitute an epitaxial wafer (100) for LEDs. It is possible to provide the pattern wafer for LEDs and epitaxial wafer for LEDs with cracks and internal quantum efficiency IQE improved.

Abstract: Light Emitting Devices (LEDs) are fabricated on a wafer substrate with one or more thick metal layers that provide structural support to each LED. The streets, or lanes, between individual LEDs do not include this metal, and the wafer can be easily sliced/diced into singulated self-supporting LEDs. Because these devices are self-supporting, a separate support submount is not required. Before singulation, further processes may be applied at the wafer-level; after singulation, these self-supporting LEDs may be picked and placed upon an intermediate substrate for further processing as required. In an embodiment of this invention, protective optical domes are formed over the light emitting devices at the wafer-level or while the light emitting devices are situated on the intermediate substrate.

Abstract: According to this GaN-based HFET, resistivity ? of a semi-insulating film forming a gate insulating film is 3.9×109?cm. The value of this resistivity ? is a value derived when the current density is 6.25×10?4 (A/cm2). By inclusion of the gate insulating film by a semi-insulating film having a resistivity ?=3.9×109?cm, a withstand voltage of 1000 V can be obtained. Meanwhile, the withstand voltage abruptly drops as the resistivity of the gate insulating film exceeds 1 ×1011?cm, and the gate leak current increases when the resistivity of the gate insulating film drops below 1 ×107?cm.

Abstract: A method is provided for producing a nitride compound semiconductor device. A growth substrate has a silicon surface. A buffer layer, which comprises AlxInyGa1-x-yN with 0?x?1, 0?y?1 and x+y?1, is grown onto the silicon surface of the substrate. A semiconductor layer sequence is grown onto the buffer layer. The buffer layer includes a material composition that varies in such a way that a lateral lattice constant of the buffer layer increases stepwise or continuously in a first region and decreases stepwise or continuously in a second region, which follows the first region in the growth direction. At an interface with the semiconductor layer sequence, the buffer layer includes a smaller lateral lattice constant than a semiconductor layer of the semiconductor layer sequence adjoining the buffer layer.

Abstract: A MEMS device. The device includes a membrane, and a reinforced backplate having a plurality of openings. The reinforced backplate include a first layer, and a second layer coupled to the first layer.

Abstract: In accordance with certain embodiments, electronic components such as light-emitting elements are bonded to connection points on a substrate via pressure applied via a membrane and curing of a pressure-activated adhesive.

Abstract: The present disclosure provides a TFT array substrate and manufacturing method thereof, forming a class structure of graphene-like two-dimensional layered semiconductor material on a base substrate and transferring the class structure of graphene-like two-dimensional layered semiconductor material on the designated position of the soft substrate to be a semiconductor active layer of the array substrate, therefore the semiconductor active layer of the TFT array substrate of the present disclosure uses a class structure of graphene-like two-dimensional layered semiconductor material to makes the array substrate having the advantage of higher electron mobility and mechanical property, excellent flexural resistance and reducing thickness of the substrate greatly.

Abstract: A laminate includes a core, a buildup layer having a top and a bottom, the bottom contacting the core and a solder mask contacting the top, the solder mask including at least one warpage control region formed on a top surface of the solder mask.

Abstract: A method for producing a P-N junction in a thin film photovoltaic cell comprising a deposition step in which are carried out successively: a layer of precursors of a photovoltaic material of type P or N, a barrier layer and a layer of precursors of a semiconducting material of type N or P, this deposition step being followed by an annealing step carried out with a supply of S and/or Se, this annealing step leading to the formation of an absorbing layer of the type P or N and of a buffer layer of type N or P and of a P-N junction at the interface between said layers.

Abstract: The present invention herein relates to a method of forming a through-hole in a silicon substrate. The present invention herein also relates to a method of forming an electrical connection element which penetrates through the silicon substrate, and to a semiconductor device manufactured thereby. More particularly, the present invention herein relates to a method of forming in a silicon substrate a through-hole capable of reducing roughness in a side wall of the through-hole and exhibiting low permittivity, by alternatingly laminating cationic and anionic polymer on the through-hole that has a dent on the side wall to form a porous elastic layer, and also relates to a method of forming an electrical connection that penetrates through the silicon substrate, and to a semiconductor device manufactured thereby.

Abstract: A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

Abstract: According to one embodiment, a semiconductor module includes a first semiconductor element, a second semiconductor element, a first light emitting element and a second light emitting element. The first semiconductor element is provided with a first light receiving circuit and a first output circuit. The second semiconductor element is provided with a second light receiving circuit and a second output circuit. The first light emitting element is electrically connected to the second output circuit and mounted on the first semiconductor element such that first light emitted from the first light emitting element is received by the first light receiving circuit. The second light emitting element is electrically connected to the first output circuit and mounted on the second semiconductor element such that second light emitted from the second light emitting element is received by the second light receiving circuit.

Abstract: A MEMS trapped membrane. The MEMS trapped membrane includes a first layer and a second structure. The first layer has an outer section and an inner membrane. The outer section and inner membrane are detached from each other by a separation, and have inner membrane protrusions and outer section protrusions formed by the separation. The second structure is coupled to the outer section and has second protrusions that overlay corresponding inner membrane protrusions.

Abstract: A method of manufacturing a light-emitting device includes forming a separation layer on an upper surface of a supporting substrate; forming a plurality of external electrode layers on the separation layer; mounting a plurality of light-emitting elements on the external electrode layers; forming a plurality of resin layers between the supporting substrate and each of the light-emitting elements after mounting the light-emitting elements, the resin layers being formed such that the resin layers are separated from one another, and each resin layer underlies at least one light-emitting element; and applying laser light to the separation layer from a lower surface side of the supporting substrate, and separating the supporting substrate and the light-emitting elements from each other.

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.

Abstract: A method for manufacturing a display device is provided including forming a light emitting element by stacking in sequence a pixel electrode, light emitting layer and common electrode above a substrate, and forming an organic material pattern including a plurality of protrusions by evaporating an organic material above the common electrode, wherein the evaporation is performed under a reduced pressure in at a substrate temperature that is equal to or less than a glass transition temperature of the organic material.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. There is prepared a first silicon carbide layer having a first main surface and a second main surface. A first recess including a side portion and a bottom portion is formed in the first main surface of the first silicon carbide layer. A second silicon carbide layer is formed in contact with the first main surface, the side portion, and the bottom portion. An image of a second recess formed at a position facing the first recess of the fourth main surface is obtained. Alignment is performed based on the image of the second recess. The first main surface corresponds to a plane angled off relative to a {0001} plane. A ratio obtained by dividing a depth of the first recess by a thickness of the second silicon carbide layer is more than 0.2.