Abstract: A manufacturing process for an integrated circuit which includes at least one vertical-current-flow MOS transistor. The patterned photoresist which screens the body implant is also used to mask the etching of a nitride layer over a pad oxide. After the photoresist is cleared, the nitride pattern is transferred into the oxide, and the resulting oxide/nitride stack is used to mask the source implant. The nitride/oxide stack is then removed, the gate oxide is grown, and the gate layer is then deposited.

Abstract: A porous film 64 is used to thermally insulate sensing integrated circuitry 44 from pixels 34 of an uncooled IR detector hybrid system 30. The porous film 64 is preferably a silicon-dioxide xerogel. A protective film 65 may be deposited on the porous film 64.

Abstract: A sensor for use in read/writing the magnetic pattern stored in a magnetic storage disk uses a Corbino structure comprising inner and outer electrodes enclosing a magnetoresistive element. The sensor is formed at the front surface of a stack of superposed layers of which the first and fifth are of a high resistivity semiconductive material, the second and fourth are of a magnetoresistive material and the third of a metal or composite structure. The second and fourth layers form a loop around the third layer, the first and fifth form a loop around the second and fourth layers. A dopant is diffused into the front surface of the stack to convert edge portions of the first and fifth layers to low resistivity to form a conductive loop that serves as the outer electrode of the Corbino disk, the third electrode serving as the inner electrode.

Abstract: A semiconductor device has a capacitive element with excellent leak current characteristics which has a tungsten film with a roughened surface for increasing the surface of a lower electrode. A capacitive element for use in a VLSI memory circuit such as a DRAM or the like is fabricated by forming a thin, roughened tungsten film selectively on a surface of a lower electrode of polysilicon by chemical vapor-phase growth and forming a capacitive insulating film on the surface of the lower electrode of polysilicon, densifying the capacitive insulating film, and forming an upper electrode of a metal element.

Abstract: A method and apparatus for forming semiconductor particles (42) for solar cells using an optical furnace (30). Uniform mass piles (26) of powered semiconductor feedstock are almost instantaneously optically fused to define high purity semiconductor particles without oxidation. The high intensity optical energy is directed and focused to the semiconductor feedstock piles (26) advanced by a conveyer medium (16) thereunder. The semiconductor feedstock piles (26) are at least partially melted and fused to form a single semiconductor particle (42) which can be later separated from a refractory layer (18) by a separator (50), preferably comprised of silica. The apparatus (10) and process is automated, providing a high throughput to produce uniform mass, high quality spheres for realizing high efficiency solar cells. The apparatus is energy efficient, whereby process parameters can be easily and quickly established.

Abstract: A method for heat-treating a semiconductor body comprising steps of: (a) disposing a susceptor on one surface of the semiconductor body, and disposing a protection plate in such a manner that the other surface of the semiconductor faces to a surface the protection plate, (b) heat-treating the semiconductor body, wherein the susceptor and the protection plate comprises at least one member selected from the group consisting of gallium nitride, aluminum nitride and boron nitride, and at least one of the susceptor and the protection plate has an absorber of infrared ray.

Abstract: A process and apparatus for manufacturing MOS devices are disclosed. The process comprises the step of controlling a first clearance linear speeds (1st CLSs) X which is the flows of an oxidizing and an annealing gases defined as ratios of the flow rates thereof to the area of a clearance between a semiconductor wafer and the interior surface of the tube of a heat treating furnace to be at least 30 cm/min while the semiconductor wafer is oxidized and annealed. The process comprises the step of controlling a second clearance linear speed (2nd CLS) Y which is a flow of the annealing gas defined as a ratio of the flow rate thereof to the area of the clearance to be at least 100 cm/min while the semiconductor wafer is taken out of the tube. The process comprises the step of controlling a relation between the 1st CLSs X and the 2nd CLS Y so that Y.gtoreq.-2.5 X+275. The process and the apparatus reduce and control the fixed-charge density in the oxide film of a MOS device with a high repeatability.

Abstract: One or more thin film layers of material may be formed on an integrated circuit substrate and anisotropically etched to produce a monolithic thermal detector. A first layer of material may be placed on the integrated circuit substrate and anisotropically etched to form a plurality of supporting structures for the thermal sensors of the associated focal plane array. The thermal sensors of the focal plane array may be provided by anisotropically etching one or more thin film layers of material formed on the supporting structures. In an exemplary thermal detector, one of the thin film layers preferably includes pyroelectric material such as barium strontium titanate. A layer of thermal insulating material may be disposed between the integrated circuit substrate and the pyroelectric film layer to allow annealing of the pyroelectric film layer without causing damage to the associated integrated circuit substrate.

Abstract: A semiconductor structure with large tile angle boron implant is provided for reducing threshold shifts or rolloff at the channel edges. By minimizing threshold shifts, short channel effects and subthreshold currents at or near the substrate surface are lessened. The semiconductor structure is prepared by implanting boron at a non-perpendicular into the juncture between the channel and the source/drain as well as the juncture between the field areas and the source/drain. Placement of boron into these critical regions replenishes segregating and redistributing threshold adjust implant species and channel stop implant species resulting from process temperature cycles. Using lighter boron ions allow for a lesser annealing temperature and thereby avoids the disadvantages of enhanced redistribution and diffusion caused by high temperature anneal.

Abstract: A thin-film semiconductor device comprising a substrate and a front contact layer disposed on said substrate including a plurality of segments separated by first scribe lines, a plurality of the segments forming a submodule, and at least one of the submodules forming a module. A bus is provided for interconnecting two or more of the submodules in parallel with each other. A thin film of a semiconductor material is disposed on the front contact layer and a back contact layer disposed on the thin film of semiconductor material. The back contact layer is scribed along second scribe lines corresponding to and adjacent the first scribe lines. An interconnection is provided for interconnecting adjacent areas of the rear and back contact layers.

Abstract: In a method of forming a buried impurity layer at a deep position of a semiconductor substrate, the resist configuration is prevented from sagging. A resist film having a film thickness of at least 3 .mu.m is formed on a semiconductor substrate. The resist film is exposed selectively to form an image. After exposure and before developing, the resist film is baked at the temperature of 110.degree.-130.degree. C. The resist film is developed and rinsed to form a resist pattern. The generated resist pattern is baked at a temperature of 100.degree. C.-130.degree. C. Using the resist pattern as a mask, impurity ions are implanted at high energy to the main surface of the semiconductor substrate to form a buried impurity layer at a deep position of the semiconductor substrate. Then, the resist pattern is removed.

Abstract: The method is a technique for making silicon-on-insulator (SOI) wafers which are suitable for use in the production of CMOS devices, which are designed to operate with low power and low voltage. The method of the invention provides high quality SOI material at relatively low cost by implanting, in one form of the invention, a very low dose of nitrogen or oxygen ions at a very low energy into silicon, and thereafter diffusing oxygen during an annealing process to form a continuous buried layer of silicon-oxy-nitride (Si.sub.x,O.sub.y N.sub.z, or SON) or SiO.sub.2. The process includes using an ion beam to implant ions into the substrate, thereby damaging a region of the crystal. The feed gas for the ion beam may be a variety of nitro-oxide gases, such as NO, N.sub.2 O, NO.sub.2, as well as a simple mixture of nitrogen and oxygen gases. Other elemental ions may be implanted to create the desired crystal defects.

Abstract: A method of preparing semiconductor wafers with intrinsic gettering capability, comprises the steps of: carrying out a high temperature wet oxidation on a doped semiconductor wafer for between about 20 to 60 minutes to form an initial oxidation layer; heating said wafer at a moderate temperature in an inert atmosphere for about 1 to 4 hours to initiate formation of crystal nuclei; ramping up the temperature in said inert atmosphere to a temperature of at least about 850.degree. C. at a rate of about 1.degree.-10.degree. C./min.; and subsequently carrying out well diffusion on the wafer at a temperature of at least about 1000.degree. C.

Abstract: A method for forming a contact hole for a metal line in a semiconductor device, including the steps of forming a contact area on a semiconductor substrate to be connected to a metal line, forming a groove, of which side is insulated from a contact portion on a bottom and at a side of the groove, forming an insulating layer on a whole surface of the semiconductor substrate, and forming a contact hole by removing a portion of the insulating layer on the barrier metal contact portion.

Abstract: A thinned backside illuminated charge-coupled imaging device has improved quantum efficiency by providing a sharp ion implant distribution profile (20) disposed at the rear surface (22) of the device. The sharp ion implant distribution profile (20) is formed using ion implantation at a beam energy potential of between 100-150 keV, which forms an electric field beneath the surface of the device. The ion distribution profile (20) is brought to the surface (22) of the device by removing silicon (18) from the rear surface (22), using a polishing technique wherein the device is lapped with colloidal silica abrasive to controllably remove silicon down to the level of the ion implantation profile (20).

Abstract: A radiation imager includes a photosensor barrier layer disposed between an amorphous silicon photosensor array and the scintillator. The barrier layer includes two strata, the first stratum being silicon oxide disposed over the upper conductive layer of the photosensor array and the second stratum is silicon nitride that is disposed over the first stratum. The photosensor barrier layer has a shape that substantially conforms to the the shape of the underlying upper conductive layer and has a maximum thickness of about 3 microns. The silicon oxide and silicon nitride are deposited in a vapor deposition process at less than about 250.degree. C. using tetraethoxysilane (TEOS) as the silicon source gas.

Abstract: A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant,, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.13 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

Abstract: An object of the present invention is to provide a highly integrated infrared detecting element array having infrared detecting elements which are disposed at a high density and have a low heat capacity each. An insulator film 2 is provided on a silicon substrate 1 having upper surface in a {100} plane; opening portions are defined by etching right-angled triangular portions defined at four corners of each of right-angled quadrilaterals arranged in matrix array and enclosed by two orthogonally crossing pairs of parallel linear portions extending on the insulator film a pyramid cavity; 3 is defined into the silicon substrate underlying the insulator film 2 by anisotropically etching the silicon substrate; and infrared detecting elements are formed on the insulator film 2.

Abstract: A semiconductor device includes a buried impurity layer formed at a predetermined depth from a main surface of a semiconductor substrate by utilizing ion injection of a conductivity type determining element, and a gettering layer formed in a position adjacent to and not shallower than the buried impurity layer by utilizing ion injection of an element other than a conductivity type determining element.

Abstract: A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12). A thick insulator layer (26) is formed on the drift region (24). An IGFET body (28) of the first conductivity type is formed adjacent the drift region (24). A source region (34) of the second conductivity type is formed within the IGFET body (28) and spaced from the drift region (24) defining a channel region (40) within the IGFET body (28). A conductive gate (32) is insulatively disposed over the IGFET body (28) and extends from the source region (34) to the thick insulator layer (26). A drain region (36) is formed adjacent the drift region (24).