Abstract: Techniques herein support enhanced multi-rate encoding and decoding of signals in multiple formats. In one embodiment, input data is received at a first device at one of a plurality of data rates. Encoder units are activated to produce streams of encoded input data. The encoder units are configured to operate at the same data rate. Differential encoding operations are performed to produce an encoded output stream. The encoded output stream is modulated for transmission to a second device. In another embodiment, a first device receives an encoded data stream that is transmitted from a second device. The modulated data stream includes encoded data at one of a plurality of data rates. Differential decoding is performed on the encoded data by activating one or more of a plurality of decoder units, where each of the plurality of decoder units is configured to operate at the same rate.

Abstract: The method includes that: a first transmission node receives a signal including a Transmission Block (TB) from a second transmission node; the first transmission node obtains states of the P CB sets according to the signal including the TB; the first transmission node determines at least one kind of feedback information in a preset feedback information set according to the states of the P CB sets; and the first transmission node sends the determined feedback information to the second transmission node.

Abstract: In one embodiment, the data storage apparatus includes a control unit configured to decode at least one input command and configured to generate at least one of a read signal and a start signal in response to the input command. The start signal indicates to start an internal mode determination process. The data storage apparatus also includes a memory unit configured to output data in response to the read signal, and a coding unit configured to start and perform the internal mode determination process in response to the start signal. The internal mode determination process includes autonomously determining a coding mode, and the coding unit is configured to code the output data based on the determined coding mode to produce coded data.

Abstract: A semiconductor device includes a usable address storage unit for selectively storing addresses of a plurality of memory sets using read data of the plurality of memory sets outputted from a nonvolatile memory during a boot-up operation; a register unit for storing the read data of the plurality of memory sets outputted from the nonvolatile memory during the boot-up operation; and an internal circuit for operating by using the read data of the plurality of memory sets stored in the register unit. Addresses corresponding to usable memory sets excluding already-used memory sets and defective memory sets among the memory sets of the nonvolatile memory are extracted and stored, and thus, although an address is not separately inputted when the nonvolatile memory is programmed, data may be programmed in a programmable (usable) memory set.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present invention relates to a method and a device for efficiently shortening and puncturing a non-binary LDPC code, the method for a transmitter shortening and puncturing a non-binary code being capable of supporting various modulation methods by using a single non-binary code, and the method comprising the steps of: shortening, on the basis of a modulation method, at least one information bit in at least one information symbol constituting the non-binary code; encoding the at least one information symbol having a shortened information bit; and puncturing, on the basis of the modulation method, at least one parity code in at least one parity symbol obtained through the encoding step.

Abstract: The present invention provides a data-storage device including a flash memory and a controller. The flash memory includes a plurality of blocks, and each of the blocks has a plurality of pages, wherein each of the pages has a plurality of sub-pages and a plurality of spare areas, each of the spare areas is arranged to store a spare data sector, and the spare data sector respectively corresponds to the sub-pages. The controller is arranged to access the sub-pages according to the spare data sector.

Abstract: A method and corresponding user equipment (UE) for configuring a circular buffer in a wireless communication system. The method includes: generating a code block including a payload, a first outer code parity, and a second outer code parity from an input signal based on an outer code in a higher layer; generating a codeword from the code block based on an inner code in a physical layer; and configuring a circular buffer including the codeword and one or more second outer code parities.

Abstract: Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.

Abstract: Embodiments of the present invention provide an encoding/decoding method, apparatus, and system. The present invention is used to improve the decoding performance and improve accuracy of a survivor path. The method includes: encoding information bits to obtain a first-level encoded code word; obtaining a sorting value of each check bit of the first-level encoded code word, and adjusting each check bit to a corresponding position according to the sorting value of each check bit, where the sorting value refers to a value of S when the check bit is related to first S information bits of the information bits in the first-level encoded code word, and S is a non-zero integer; and performing second-level encoding on the first-level encoded code word after positions of the check bits are adjusted, thereby obtaining a second-level encoded code word. The present invention is applicable to various communication systems.

Abstract: A turbo decoder system decodes L-length digital data consisting of a systematic code and 1st and 2nd parity check codes, and includes a trellis controller obtaining the ratio of the bit-number Ep of the 1st/2nd parity check code to the bit-number D of an original systematic code and generating, based on the code rate of the digital data, a trellis control output indicating a target decoding trellis, which is selected by a turbo decoder to perform decoding operations. A zero-patch module patches zeros into the systematic code, and patches, based on the value of Ep/D, one or more zeros into the 1st/2nd parity check code so that parity check bits of the 1st/2nd parity check code and the zero-bit(s) form a periodically depunctured parity check code.

Abstract: Some demonstrative embodiments include apparatus, system and method of communicating a transmission encoded according to a Low-Density Parity-Check (LDPC) code. For example, an apparatus may include logic and circuitry configured to cause a wireless station to encode a plurality of data bits into a plurality of codewords according to an LDPC code having an encoding rate of 7/8 and a codeword length of 1248 bits; and to transmit a transmission over a millimeter Wave (mmWave) frequency band based on the plurality of codewords.

Abstract: A system includes a code rate selecting module and a matrix generating module. The code rate selecting module is configured to select a code rate of k/n to encode k units of data into n units of data using a low-density parity-check (LDPC) code, where k and n are integers greater than 1, and k<n. The matrix generating module is configured to generate a matrix with (R+S) rows and (C+S) columns, where R and C are integers greater than 1, R=C/n, and S is an integer greater than or equal to zero and denotes a number of columns of the matrix deleted after encoding the k units of data using the LDPC code.

Abstract: A memory test data generating circuit and method for generating a plurality of sets of test data is provided. The plurality of sets of test data is provided to a memory via a plurality of channels by a memory controller and is for testing the memory. The memory test data generating circuit includes: a plurality of counters, generating a plurality of counter values; and a data repetition and combination unit, generating the plurality of sets of test data according to the plurality of counter values, a bit width between the memory test data generating circuit and the memory controller, and a bit width between the memory controller and the memory. The test data of each channel is an identical and periodical data series.

Abstract: Systems and methods are provided for decoding a codeword of a low density parity check (LDPC) code. The systems and methods may include receiving a vector corresponding to the codeword encoded with a parity check matrix, and processing a first portion of the received vector with a first portion of the parity check matrix to obtain a decoding estimate of a first portion of the codeword. The systems and methods may further include processing the decoding estimate of the first portion of the codeword with a second portion of the parity check matrix to obtain an intermediate vector, and processing a second portion of the received vector with a third portion of the parity check matrix and the intermediate vector to obtain a decoding estimate of a second portion of the codeword.

Abstract: The method includes code block segmentation is performed on a physical layer source data packet, to be sent, having a length of Ks bits, and channel coding is performed on each code block obtained by segmentation, to obtain Cs error-corrected and coded source data sub-packets having lengths of Kc bits; packet coding is performed on the error-corrected and coded source data sub-packets, to obtain Cp check data sub-packets; Ki codeword bits are selected from the ith sub-packet in Cs source data sub-packets, Kj codeword bits are selected from the jth sub-packet in the Cp check data sub-packets, all the selected bits are cascaded together to form a sequence having a length of formula (I), i=0, 1, . . . , Cs?1, j=0, 1, . . . , Cp?1, and the sequence is sent, herein Ks, Cs and Kc are integers greater than 1, and Cp, Ki and Kj are integers greater than or equal to 0.

Abstract: A request associated with modifying the original data to be new data is received. A difference between the original data and the new data is determined. Erasure coding is performed using the difference between the original data and the new data to obtain a parity difference. The original parity is updated using the parity difference.

Abstract: Methods and apparatus for accessing dispersed storage error encoded data in a dispersed storage network (DSN). When storing data in available storage units of a DSN, a DS processing unit issues a write slice request that includes a slice name corresponding to the storage unit and a unique encoded data slice of the set of encoded data slices, where each encoded data slice includes an IDA index of the corresponding storage unit. For each unavailable storage unit, the DS processing unit issues a write imposter slice request to a foster storage unit that includes a slice name corresponding to the foster storage unit and imposter encoded data slice corresponding to the unavailable storage unit, where the imposter encoded data slice includes an IDA index corresponding to the unavailable storage unit.

Abstract: A dispersed storage network (DSN) includes a processing unit and multiple storage unit sets. A first storage unit set and a second storage unit set receive, sets of encoded data slices generated, by the DS processing unit, for storage. The encoded data slices include dispersal-encoded portions of one or more data objects. The first and second storage unit sets are used to mirror storage of the one or more data objects. The first storage unit set stores data slices unsynchronized to the second storage unit set, and generates a record identifying the unsynchronized data slices. Later, the storage unit detects that the availability of at least one storage unit of the second storage unit set, and in response facilitates copying of particular unsynchronized data slices to corresponding storage units of the second storage unit set. After copying, the record is updated to indicate the synchronization.

Abstract: In a method of operating a nonvolatile memory device, a plurality of pages of a first memory block of a plurality of memory blocks of a memory cell array are programmed. After programming, a dummy pulse is applied to at least some of the plurality of memory blocks at least once before a read operation on is performed on one of the plurality of pages.

Abstract: Communication apparatus includes an input circuit, which receives a sequence of symbols arranged in a series of data blocks, including data symbols that encode the data and forward error correction (FEC) symbols that encode an error correction code. The input circuit decodes the data encoded by the data symbols and passes the decoded data to a buffer for output to a data link layer interface irrespective of the FEC symbols. An error correction circuit receives the data and the error correction code from the input circuit, and upon detecting an error in a given data block in the series, passes the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer.