Abstract: Embodiments of the invention are directed to systems, methods, and computer program products for aggregation and transformation of real-time data. The system is configured for retrieving data associated with the first user interaction in real-time via an established communication link with one or more interaction channels accessible to the first user; processing the data to identify a pattern associated with the first user interaction; identifying an error associated with at least a portion of the data; determining a time stamp and an interaction channel associated with the portion of data identified to be in error; replaying the data associated with the first user interaction; process the portion of data identified to be in error to rectify the error; and storing the transformed portion of data in the database.

Abstract: A memory subsystem enables managing error correction information. A memory device internally performs error detection for a range of memory locations, and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device can provide the error result to an associated host of the system to expose only a number of errors accumulated without exposing internal errors from prior to incorporation into a system. The memory device can be made capable to generate internal addresses to execute commands received from the memory controller. The memory device can be made capable to reset the counter after a first pass through the memory area in which errors are counted.

Abstract: Systems and methods are disclosed for providing operating system independent error control in computing devices. One embodiment is a method comprising: defining with a reliability, availability and serviceability (RAS) controller a first memory region for correctable errors and a second memory region for uncorrectable errors; receiving an error indication at the RAS controller; determining with the RAS controller whether the received error indication is a correctable error; and in response to the determination, if the received error indication is a correctable error, writing with the RAS controller information about the correctable error to the first memory region, and if the received error indication is an uncorrectable error, writing with the RAS controller information about the uncorrectable error to the second memory region and sending an interrupt request from the RAS controller to an operating system executing on a processor.

Abstract: A data storage device includes a controller and a non-volatile memory coupled to the controller. The controller is configured to generate first parity information based on first data and to generate second parity information based on second data. The non-volatile memory is configured to store the first data and the second data. The data storage device also includes a buffer configured to store the first parity information. The controller is further configured to generate joint parity information associated with the first data and the second data in response to a combined data size of the first data and the second data satisfying a threshold.

Abstract: Example apparatus and methods provide improved reclamation, garbage collection (GC) and defragmentation (defrag) for data storage devices including solid state drives (SSD) or shingled magnetic recording (SMR) drives. An erasure code (EC) layer that facilitates logically or physically erasing data from the SSD or SMR as a comprehensive GC or defrag is added to the SSD or SMR. Erased data may be selectively recreated from the EC layer as needed. Pre-planned EC write zones may be established to further optimize GC and defrag. Recreated data may be written to selected locations to further optimize SSD and SMR performance. Erasure code data may be distributed to co-operating devices to further improve GC or defrag. Example apparatus and methods may also facilitate writing data to an SMR drive using tape or VTL applications or processes and providing a pseudo virtual tape library on the SMR drive.

Abstract: A semiconductor device includes a non-volatile memory unit, a data line configured to transfer data sequentially outputted from the non-volatile memory unit, and a shift register unit configured to include a plurality of registers that shift and store the data transferred through the data line in synchronization with a clock. The semiconductor device includes a non-volatile memory unit having an e-fuse array, and transfers the data stored in an e-fuse array to other constituent elements of the semiconductor device that use the data of the e-fuse array in order to have the data stored in the e-fuse array, including diverse setup information and repair information.

Abstract: A circuit includes don't-care a code-value calculation circuit to calculate third code-values by coding a signal sequence in accordance with a coding scheme; a first sequence-detection circuit to detect a first sequence based on comparison of a first code-value with a difference between the current third code-value and a fourth code-value that is the third code-value preceding the current third code-value by a length of the first sequence; an expected-value calculation circuit to calculate an expected value of the third code-value at the end of the third sequence based on a second code-value and a fifth code-value that is one of the third code-values; and a determination circuit to detect the end of the second sequence based on a length of a fourth sequence, notify an expected-value calculation circuit of the detection of the second sequence, and output a detection signal indicating detection of a detection-target sequence.

Abstract: Techniques herein support enhanced multi-rate encoding and decoding of signals in multiple formats. In one embodiment, input data is received at a first device at one of a plurality of data rates. Encoder units are activated to produce streams of encoded input data. The encoder units are configured to operate at the same data rate. Differential encoding operations are performed to produce an encoded output stream. The encoded output stream is modulated for transmission to a second device. In another embodiment, a first device receives an encoded data stream that is transmitted from a second device. The modulated data stream includes encoded data at one of a plurality of data rates. Differential decoding is performed on the encoded data by activating one or more of a plurality of decoder units, where each of the plurality of decoder units is configured to operate at the same rate.

Abstract: A receiver, transmitter and method for early packet header verification are provided. In one embodiment, the method includes: (1) receiving a payload flit of a preceding packet and a header flit of a current packet; and (2) using a Cyclic Redundancy Check (CRC) in the header flit to verify the payload flit of the preceding packet and the header flit of the current packet.

Abstract: A data processing stage is described which has a communications interface arranged to receive a plurality of input data chunks. Each input data chunk has a pointer to a validation record, where the validation records are stored at a memory accessible to the data processing stage. A processor of the data processing stage is configured to create an output validation record at the memory, and to link the output validation record to the validation records of the input chunks. The processor is configured to compute an output chunk from the input chunks in a manner which ignores data of the input chunks identified as invalid through inspection of the output validation record.

Abstract: A receiver, such as a mobile station or base station, includes a sliding window-decoder. An antenna in the receiver is configured to receive a protograph-based spatially coupled low density parity check (SC-LDPC) code from a transmitter. The sliding window-decoder is configured to perform a SC-LDPC decoding operation on the SC-LDPC code using a sliding window. The SC-LDPC code includes a parity check matrix. The sliding window includes a subset of protograph sections on which decoding calculations are iteratively performed. The sliding window-decoder performs a stopping rule configured to cease the decoding calculations as a function of a syndrome of one or more check nodes (CNs) in the sliding window.

Abstract: A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields.

Abstract: A data storage device includes a memory including a plurality of storage elements. The data storage device further includes a controller coupled to the memory. The controller includes an error correction code (ECC) engine. The controller further includes a reliability engine configured to access historical bit error data. The historical bit error data includes a first count of bit errors associated with a first set of storage elements of the plurality of storage elements. The reliability engine is configured to generate reliability information based on the historical bit error data and to provide the reliability information to the ECC engine.

Abstract: A method of operating a data processing system comprises: processing data words and switching between contexts; assigning a context signature Sig to any pair formed of a data word and a context; reading, within a current context, a data record from a memory unit, the data record comprising a payload data word and a protection signature; providing, as a verification signature, the context signature Sig of the payload data word and the current context; checking the verification signature against the protection signature; and generating an error signal if the verification signature differs from the protection signature.

Abstract: Devices and methods implemented therein in are disclosed for correcting errors in data. The method comprises determining that a first copy of data and a second copy of data include errors uncorrectable by an error correction code (ECC) engine. The ECC engine is modified based on determining that the first copy of data and the second copy of data include errors uncorrectable by the ECC engine and using the modified ECC engine, the first copy of data and the second copy of data are processed to correct the errors in the first and second copy of the data.

Abstract: A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a metadata manager that offloads metadata management from the other system components. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the devices external to the stacked memory device. The memory interface operates to perform memory accesses for the external devices and for the metadata manager. By virtue of the metadata manager's tight integration with the stacked memory layers, the metadata manager may perform certain memory-intensive metadata management operations more efficiently than could be performed by the external devices.

Abstract: A memory module (735) can include a memory array (105) and a memory controller (740). The memory controller (740) can include a status register (745) that specifies whether the memory module (735) is operating at normal power or low power. A normal reliability region (305, 505) and a low reliability region (310, 510) can be defined in the memory array (105), based on the power level specified by the status register (745).

Abstract: Classifying memory errors may include accessing data from a location within a memory array of a memory device. The memory array may include at least one bit field to store memory error classification information. One or more memory errors in the data may be determined. One or more memory errors may further be classified. In response to the classifying, memory error classification information may be stored as one or more bit values within the bit field.

Abstract: According to one embodiment, a search device includes a first comparison module, a determination module, a correction module, a second comparison module, and a search module. The first comparison module compares a received first key with a second key read from a nonvolatile memory. The determination module determines whether error correction is possible based on a first comparison result obtained by the first comparison module. The correction module generates a third key by applying an error correction process to the second key if the determination module determines that error correction is possible. The second comparison module compares the first key with the third key. The search module reads data associated with the second key in the nonvolatile memory if a second comparison result obtained by the second comparison module shows a match.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.