Abstract: Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of lead fingers without encapsulating a microelectronic device. The encapsulating compound can generally fill the plurality of gaps between two adjacent lead fingers.

Abstract: The method for producing a pillar-shaped semiconductor device includes a step of providing a structure that includes, on an i layer substrate, a Si pillar and an impurity region located in a lower portion of the Si pillar and serving as a source or a drain, a step of forming a SiO2 layer that extends in a horizontal direction and is connected to an entire periphery of the impurity region in plan view, a step of forming a SiO2 layer on the SiO2 layer such that the SiO2 layer surrounds the Si pillar in plan view, a step of forming a resist layer that is partly connected to the SiO2 layer in plan view, and a step of forming a SiO2 layer by etching the SiO2 layer below the SiO2 layer and the resist layer using the SiO2 layer and the resist layer as masks.

Abstract: Described herein are various amorphous metal thin film transistors. Embodiments of such transistors include an amorphous metal gate electrode and a channel conductor formed on a non-conducting substrate. Further embodiments of such transistors include an amorphous metal source electrode, an amorphous metal drain electrode, and a channel conductor formed on a non-conducting substrate. Methods of forming such transistors are also described.

Abstract: The present disclosure relates to a thin film transistor. The thin film transistor may include a substrate, a source electrode on the substrate, a drain electrode on the substrate, a gate on the substrate, and an active layer on the substrate. The source electrode may include a first teeth portion. The drain electrode may include a second teeth portion. The gate may include a third teeth portion. The active layer may include a plurality of channel regions. The first teeth portion, the second teeth portion, the third teeth portion, and the active layer form a plurality of sub-thin film transistors connected in parallel. The center sub-thin film transistor has a channel region having a smallest width-to-length ratio among the plurality of sub-thin film transistors.

Abstract: Methods are disclosed herein for forming fin-like field effect transistors (FinFETs) that maximize strain in channel regions of the FinFETs. An exemplary method includes forming a fin having a first width over a substrate. The fin includes a first semiconductor material, a second semiconductor material disposed over the first semiconductor material, and a third semiconductor material disposed over the second semiconductor material. A portion of the second semiconductor material is oxidized, thereby forming a second semiconductor oxide material. The third semiconductor material is trimmed to reduce a width of the third semiconductor material from the first width to a second width. The method further includes forming an isolation feature adjacent to the fin. The method further includes forming a gate structure over a portion of the fin, such that the gate structure is disposed between source/drain regions of the fin.

Abstract: There is provided a white light emitting device comprising a first LED and a second LED disposed on a substrate, a first photoluminescence material layer disposed over at least said first LED, a second photoluminescence material layer disposed over at least said second LED, and a diffusing layer disposed over said first and second photoluminescence layers, said diffusing layer comprising light scattering particles. A method and component are also provided.

Abstract: A first solid-state imaging element according to an embodiment of the present disclosure includes a bottom-electrode; a top-electrode opposed to the bottom-electrode; a photoelectric conversion layer provided between the bottom-electrode and the top-electrode and including a first organic semiconductor material; and an—upper inter-layer provided between the top-electrode and the photoelectric conversion layer, and including a second organic semiconductor material having a halogen atom in a molecule at a concentration in a range from 0 volume % or more to less than 0.05 volume %.

Abstract: Techniques regarding one or more VFETs operably coupled to bottom contacts with low electrical resistance are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a vertical field-effect transistor device that can comprise a semiconductor fin positioned on a source/drain region, which can comprise a semiconductor substrate. The apparatus can also comprise a metal contact layer positioned on the source/drain region and at least partially surrounding a base of the semiconductor fin. Further, the metal contact layer can be in electrical communication with the source/drain region.

Abstract: Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.

Abstract: One illustrative method of forming heterojunction bipolar devices includes, among other things, forming a first gate structure above an active semiconductor layer, forming a second gate structure adjacent a first side of the first gate structure, forming a third gate structure adjacent a second side of the first gate structure, forming an emitter of a bipolar transistor in the active semiconductor layer between the first gate structure and the second gate structure, forming a collector of the bipolar transistor in the active semiconductor layer between the first gate structure and the third gate structure, and forming a first base contact contacting the active region adjacent an end of the first gate structure, wherein a portion of the active semiconductor layer positioned under the first gate structure defines a base of the bipolar transistor.

Abstract: A semiconductor device has a semiconductor substrate that includes an element range and a peripheral range. The semiconductor substrate includes: a body region disposed within the element range; a p-type deep region that is disposed from the element range through the peripheral range, is distributed from an upper surface of the semiconductor substrate to a position deeper than a lower end of each gate trench, and involves end gate trench; and a p-type voltage resistance region that is disposed within the peripheral range, and is distributed from the upper surface to a position shallower than a lower end of the p-type deep region. A p-type impurity concentration within the p-type deep region is increased in the direction from the body region toward the p-type voltage resistance region.

Abstract: A semiconductor device includes: a wire including a first conductive member disposed at a semiconductor substrate and a second conductive member disposed at a surface of the first conductive member, the second conductive member having an ionization tendency less than the first conductive member, wherein the first conductive member includes a first surface disposed close to the second conductive member and having a width smaller than a width of a second surface of the first conductive member which is disposed close to the semiconductor substrate, and wherein the second conductive member has a width larger than the width of the first surface of the first conductive member and smaller than the width of the second surface of the first conductive member.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: A semiconductor device includes a first conductivity type semiconductor layer including an active cell portion and an outer peripheral portion around the active cell portion, a second conductivity type body region selectively formed at a surface portion of the semiconductor layer in the active cell portion, a first conductivity type source region formed at an inner part of the body region, a gate electrode that faces a part of the body region through a gate insulating film, a second conductivity type column layer straddling a boundary between the active cell portion and the outer peripheral portion inside the semiconductor layer such that the column layer is disposed at a lower part of the body region in the active cell portion, a source electrode that is electrically connected to the source region, and an outer peripheral electrode that is electrically connected to the column layer in the outer peripheral portion.

Abstract: Disclosed are a pixel element, a method for fabricating same, a display control method, a display panel. The pixel element includes a base substrate, display and non-display areas on the base substrate, a control electrode, an adjustment layer, a transparent electrode in the non-display area, the transparent electrode and the adjustment layer are arranged in a stack, the control electrode is at the interface between display and non-display areas, and surrounds the adjustment layer, and there is a gap area between the control electrode and the adjustment layer; and the adjustment layer includes charged particles configured to move to the control electrode and the transparent electrode under control of first and second electric fields, the first and second electric fields are created after signals are applied to the control electrode and the transparent electrode, and direction of the first electric field is opposite to direction of the second electric field.

Abstract: The disclosure is directed to spin-orbit torque (“SOT”) magnetoresistive random-access memory (“MRAM”) (“SOT-MRAM”) structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a shallow trench isolation (STI) region on a well region of a substrate, a plurality of transistors, and a power rail. Each of the transistors includes at least one fin, a gate electrode formed on the fin, and a doping region formed on the fin. The fin is formed on the well region, and is extending in a first direction. The gate electrode is extending in a second direction that is perpendicular to the first direction. The power rail is formed in the STI region and below the doping regions of the transistors, and extending in the first direction. Each of the doping regions is electrically connected to the power rail, so as to form a source region of the respective transistor. The power rail is electrically connected to the well region of the substrate.

Abstract: A crystal of a group 13 nitride has an upper surface and lower surface and is composed of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride or the mixed crystals thereof. When the upper surface of the layer of the crystal of the group 13 nitride is observed by cathode luminescence, the upper surface includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part. A half value width of reflection at the (0002) plane of a X-ray rocking curve on the upper surface is 3000 seconds or less and 20 seconds or more.

Abstract: A TFT and a method for manufacturing the TFT, an array substrate, and a display device are provided. An active layer of the TFT includes a channel region, a first conductive region and a second conductive region, and the channel region is arranged between the first conductive region and the second conductive region. The channel region includes a first side and a second side, the first side is opposite to the second side, the first side is in contact with a third side of the first conductive region, the second side is in contact with a fourth side of the second conductive region, and a length of the first side is greater than a length of the third side.