Abstract: An electrical contacting between a surrounding wiring and a conductor region. The conductor region is situated in a conductor layer above an SOI wafer or SOI chip. A cover layer is situated above the conductor layer and below the surrounding wiring. The cover layer has a contacting region. The contacting region is insulated from the rest of the cover layer by a first configuration of recesses. An opening is formed at least in the contacting region. A metallic material is situated in the opening. The metallic material connects the surrounding wiring and the conductor region.

Abstract: Described herein are the design and fabrication of Group III trioxides, such as ?-Ga2O3, trench-MOS barrier Schottky (TMBS) structures with high voltage (>1 kV), low leakage capabilities, while addressing on the necessary methods to meet the requirements unique to Group III trioxides, such as ?-Ga2O3.

Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a source structure, a stacked conductive layer that overlaps with the source structure, a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer, a stacked insulating layer disposed between the first and second select conductive layers and the stacked conductive layer, and a separation insulating structure provided between the first select conductive layer and the second select conductive layer.

Abstract: A quantum dot includes a core and a plurality of shell layers surrounding the core. The core has a band gap less than that of the outermost shell layer, and the outermost shell layer has a band gap less than that of a second shell layer. Thus, a light emitting device including the quantum dot according to an embodiment may have an improved lifespan of the device and excellent luminous efficiency characteristics.

Abstract: Semiconductor fabrication method for manufacturing an interconnect structure is provided. The semiconductor fabrication method for manufacturing an interconnect structure includes providing a substrate structure comprising a substrate, a first dielectric layer on the substrate, and a metal interconnect line extending through the first dielectric layer; removing a portion of the first dielectric layer on the metal interconnect line to form a recess exposing a surface of the metal interconnect line; forming a graphene layer on the exposed surface of the metal interconnect line; and forming a second dielectric layer filling the recess and covering the graphene layer.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: A novel material is provided. A composite oxide semiconductor in which a first region and a plurality of second regions are mixed is provided. Note that the first region contains at least indium, an element M (the element M is one or more of Al, Ga, Y, and Sn), and zinc, and the plurality of second regions contain indium and zinc. Since the plurality of second regions have a higher concentration of indium than the first region, the plurality of second regions have a higher conductivity than the first region. An end portion of one of the plurality of second regions overlaps with an end portion of another one of the plurality of second regions. The plurality of second regions are three-dimensionally surrounded with the first region.

Abstract: A memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

Abstract: A flexible display device including a substrate, a light emitting layer, a first insulating layer, and a conductive layer. The substrate includes a bent region and a non-bent region. The light emitting layer overlaps the non-bent region. The first insulating layer is disposed on the substrate. The conductive layer is disposed on the first insulating layer. A sidewall of the first insulating layer includes a first tapered surface. The first tapered surface includes at least three curved surface portions continuously arranged with one another.

Abstract: A chip-scale package type light emitting diode includes a first conductivity type semiconductor layer, a mesa, a second conductivity type semiconductor layer, a transparent conductive oxide layer, a dielectric layer, a lower insulation layer, a first pad metal layer, and a second pad metal layer, an upper insulation layer. The upper insulation layer covers the first pad metal layer and the second pad metal layer, and includes a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer. The openings of the dielectric layer include openings that have different sizes from one another.

Abstract: According to an embodiment, a semiconductor device includes a first electrically conductive portion, a first semiconductor chip of a reverse-conducting insulated gate bipolar transistor, a second electrically conductive portion, a third electrically conductive portion, a second semiconductor chip of an insulated gate bipolar transistor, and a fourth electrically conductive portion. The first semiconductor chip includes a first electrode and a second electrode. The first electrode is electrically connected to the first electrically conductive portion. The second electrically conductive portion is electrically connected to the second electrode. The third electrically conductive portion is electrically connected to the first electrically conductive portion. The second semiconductor chip includes a third electrode and a fourth electrode. The third electrode is electrically connected to the third electrically conductive portion.

Abstract: A method of manufacturing a display module includes: providing a carrier substrate; providing a base layer, where a display area and a pad area are defined, on the carrier substrate; providing a circuit layer on the display area of the base layer and the pad area of the base layer; forming a though hole in the circuit layer and the base layer on the pad area; forming a conductive part by providing a conductive material from an upper surface of the circuit layer to the though hole formed in the pad area; and providing a circuit member electrically connected to the circuit layer below the base layer.

Abstract: A semiconductor device is preferably excellent in characteristics such as a loss characteristic. Provided is a semiconductor device including a semiconductor substrate, including an upper-surface electrode provided on an upper surface of the semiconductor substrate; an lower-surface electrode provided on a lower surface of the semiconductor substrate; a transistor portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; a first diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; and a second diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode, wherein the first diode portion and the second diode portion have different resistivities in a depth direction of the semiconductor substrate.

Abstract: A method of manufacturing a semiconductor structure includes following operations. A substrate is provided. A first die is disposed over the substrate. A second die is provided. The second die includes a via extended within the second die. The second die is disposed over the substrate. A molding is formed around the first die and second die. An interconnect structure is formed. The interconnect structure includes a dielectric layer and a conductive member. The dielectric layer is disposed over the molding, the first die and the second die. The conductive member is surrounded by the dielectric layer. The via is formed by removing a portion of the second die to form a recess extended within the second die and disposing a conductive material into the recess.

Abstract: A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.

Abstract: A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming an opening passing through the stack, forming a memory layer in the opening, forming a slit passing through the stack and exposing the first material layers and the second material layers, and forming first barrier patterns, without removing the second material layers, by partially oxidizing the memory layer through the second material layers.

Abstract: A semiconductor structure includes a first inductor, a second inductor, and a first input/output (I/O) pad. The first I/O pad is coupled to the first inductor and the second inductor. The first I/O pad, a first central axis of a first magnetic field of the first inductor, and a second central axis of a second magnetic field of the second inductor are disposed sequentially along a first direction.

Abstract: Light emitting diodes (“LEDs”) with N-polarity and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a light emitting diode on a substrate having a substrate material includes forming a nitrogen-rich environment at least proximate a surface of the substrate without forming a nitrodizing product of the substrate material on the surface of the substrate. The method also includes forming an LED structure with a nitrogen polarity on the surface of the substrate with a nitrogen-rich environment.

Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The second insulating film comprises a silicon oxynitride film. When excess oxygen is added to the second insulating film by oxygen plasma treatment, oxygen can be efficiently supplied to the oxide semiconductor film.

Abstract: Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a ferroelectric memory cell includes a first electrode, a second electrode, and a ferroelectric layer disposed between the first electrode and the second electrode. An edge region exposed by the first electrode and the second electrode is covered by at least one of a healing layer or a block layer.