Abstract: A flash memory device includes a flash memory and a buffer memory. The flash memory is divided into a main region and a spare region. The buffer memory is a random access memory and has the same structure as the flash memory. In addition, the flash memory device further includes control means for mapping an address of the flash memory applied from a host so as to divide a structure of the buffer memory into a main region and a spare region and for controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory.

Abstract: A write-once optical disc and a method and apparatus for recording management information on the disc are provided. The method includes recording an opened SRR information on a recording medium, and removing an identification of a certain SRR from the opened SRR information once the certain SRR is closed. The opened SRR information carries an identification of any opened SRR, and the number of opened SRRs allowed is at most a predetermined number.

Abstract: Multi-processor systems and methods are disclosed that employ a pre-fetch buffer to provide data fills to a source processor in response to a request. A pre-fetch buffer retrieves data as a uncached data fill. The source processor processes the data in response to a source request.

Abstract: In one embodiment of the present invention, a method and system are provided to control access to the non-volatile log (NVlog) of a storage server. By controlling access to the NVLog of a storage server the relative disk write bandwidth available to different client write requests can be controlled. The incoming write request can be categorized, and, during times of heavy load, only be permitted to use NVLog space as permitted based on the categorization of each write request. In one embodiment, the present invention includes receiving a write request from a client at a storage server, and determining whether the received write request can be presently logged in a NVlog based on a category of the write request.

Abstract: A performance monitor reports SAN performance so that issues within the SAN are not masked from the client. Accesses to the SAN may be grouped into the categories of SAN logical or SAN physical. In one specific embodiment, the ranges of service times for accesses to the SAN are determined by monitoring service times of accesses to the SAN from the client perspective. In another specific embodiment, the ranges of service times for the SAN are determined by the SAN returning data with each request that indicates the service time from the SAN perspective. This allows reporting not only SAN logical and SAN physical accesses, but also allows reporting SAN service time. By specifying SAN service time, the client is able to better determine network delays. In yet another embodiment, information is returned by the SAN to indicate whether the access is SAN logical or SAN physical.

Abstract: Method and apparatus for flushing cached writeback data to a storage array. Sets of writeback data are accumulated in a cache memory in an array with a view toward maintaining a substantially uniform distribution of the data across different locations of the storage array. The arrayed sets of data are thereafter transferred from the cache memory to the storage array substantially at a rate at which additional sets of writeback data are provided to the cache memory by a host. Each set of writeback data preferably comprises a plurality of contiguous data blocks, and are preferably written (flushed) to the storage in conjunction with the operation of a separate access command within a selected proximity range of the data with respect to the storage array. A stripe data descriptor (SDD) is preferably maintained for each set of writeback data in the array.

Abstract: A mechanism is provided for providing an improved reconfigurable cache. The mechanism partitions a large cache into inclusive cache regions with equal-ratio size or other coarse size increase. The cache controller includes an address decoder for the large cache with a large routing structure. The cache controller includes an additional address decoder for the small cache with a smaller routing structure. The additional address decoder for the small cache reduces decode, array access, and data return latencies. When only a small cache is actively in use, the rest of the cache can be turned into low-power mode to save power.

Abstract: The disclosure relates to techniques for locking and unlocking cache lines in a cache included within a multi-media processor that performs read-modify-write functions using batch read and write requests for data stored in either an external memory or an embedded memory. The techniques may comprise receiving a read request in a batch of read requests for data included in a section of a cache line and setting a lock bit associated with the section in response to the read request. When the lock bit is set, additional read requests in the batch of read requests are unable to access data in that section of the cache line. The lock bit may be unset in response to a write request in a batch of write requests to update the data previously read out from that section of the cache line.

Abstract: Provided is a computer system including: a host computer; a first storage system connected to the host computer; and a second storage system connected to the first storage system; in which the first storage system sets a first logical volume recognized by the host computer as a logical storage area; the first logical volume includes a plurality of first storage areas; a first real storage area on the first disk drive is allocated to at least one of the first storage areas. In the computer system, the second storage system sets a second logical volume corresponding to the first logical volume, and the first storage system transmits data stored in the first storage area allocated to the first storage area to the second storage system when the first real storage area is allocated to the first storage area.

Abstract: Apparatus and method for employing a Hardware Processing Function in a processor system using a hierarchical memory. Embodiments of the disclosed invention may be used to enhance processor performance and functionality while maintaining cache coherency and reducing cache pollution. A system includes a processor, a hierarchical memory system coupled to the processor, and a Hardware Processing Function coupled to the hierarchical memory system. The processor is configured to decode an instruction and the hierarchical memory system is configured to execute the instruction. The instruction directs the memory system to perform a data manipulation. The processor transfers a value to the memory system. The value comprises a location of source data to be manipulated, a selection of a Hardware Processing Function to perform the data manipulation, and a destination storage location where the manipulated data is to be stored.

Abstract: A storage system condition indicator and method provides a visual display representing the operating condition of a set of storage devices. Various operating conditions may be defined based on available storage capacity and capacity to store data redundantly. One or more indicators may be used to represent the operating condition of the set of storage devices. The indicator(s) may be used to indicate whether additional storage capacity is recommended and, in a storage array, which slot in the array should be updated with additional storage capacity.

Abstract: A non-volatile memory device is operated by outputting data in response to an alternating sequence of first and second edges of a read control signal, respectively. A determination is made whether the read control signal and a write control signal are in synchronization at one of the first edges. Output of the data is stopped at the second edge that follows the one of the first edges of the read control signal if the read control signal and the write control signal are in synchronization at the one of the first edges.

Abstract: A performance monitor reports SAN performance so that issues within the SAN are not masked from the client. Accesses to the SAN may be grouped into the categories of SAN logical or SAN physical. In one specific embodiment, the ranges of service times for accesses to the SAN are determined by monitoring service times of accesses to the SAN from the client perspective. In another specific embodiment, the ranges of service times for the SAN are determined by the SAN returning data with each request that indicates the service time from the SAN perspective. This allows reporting not only SAN logical and SAN physical accesses, but also allows reporting SAN service time. By specifying SAN service time, the client is able to better determine network delays. In yet another embodiment, information is returned by the SAN to indicate whether the access is SAN logical or SAN physical.

Abstract: A physically distributed cache memory system includes an interconnection network, first level cache memory slices, and second level cache memory slices. The first level cache memory slices are coupled to the interconnection network to generate tagged ordered store requests. Each tagged ordered store requests has a tag including requester identification and a store sequence token. The second level cache memory slices are coupled to the interconnection network to execute ordered store requests in-order across the physically distributed cache memory system in response to each tag of the tagged ordered store requests.

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, mechanisms, and means for a storage controller (e.g., memory controller, disk controller, etc.) performing a set of multiple operations on cached data with a no-miss guarantee until the multiple operations are complete, which may, for example, be used by a packet processor to quickly update multiple statistics values (e.g., byte, packet, error counts, etc.) based on processed packets. Operations to be performed on data at the same address and/or in a common data structure are grouped together and burst so that they arrive at the storage system in contiguous succession for the storage controller to perform. By not allowing the storage controller to flush the data from its cache until all of the operations are performed, even a tiny cache attached to the storage controller can reduce the bandwidth and latency of updating the data.

Abstract: Provided are a method, system, and program for destaging a track from cache to a storage device. The destaged track is retained in the cache. Verification is made of whether the storage device successfully completed writing data. Indication is made of destaged tracks eligible for removal from the cache that were destaged before the storage device is verified in response to verifying that the storage device is successfully completing the writing of data.

Abstract: A method for safeguarding data stored in a memory of a data storage system includes monitoring values of a subset of environmental variables associated with the data-storage system and updating a portion of a table containing values of environmental variables associated with the data-storage system. The table includes values for environmental variables that are not in the subset of environmental variables monitored. The values of the environmental variables are then inspected. On the basis of the inspection, a condition in which there exists a high-risk of data loss is determined.

Abstract: One embodiment of the present invention provides a system that uses versioned pointers to facilitate reusing memory without having to reclaim the objects solely through garbage collection. The system operates by first receiving a request to allocate an object. Next, the system obtains the object from a pool of free objects, and sets an allocated/free flag within the object to indicate that the object is allocated. The system also increments a version number within the object, and also encodes the version number into a pointer for the object. The system then returns the pointer, which includes the encoded version number. In this way, subsequent accesses to the object through the pointer can compare the version number encoded in the pointer with the version number within the object to determine whether the object has been reused since the pointer was generated.

Abstract: A method and mechanism are managing caches. A cache is configured to store blocks of data based upon predictions of future accesses. Each block is partitioned into sub-blocks, and if it is predicted a given sub-block is unlikely to be accessed, the sub-block may not be stored in the cache. Associated with each block is a mask which indicates whether sub-blocks of the block are likely to be accessed. When a block is first loaded into the cache, the corresponding mask is cleared and an indication is set for the block to indicate a training mode for the block. Access patterns of the block are then monitored and stored in the mask. If a given sub-block is accessed a predetermined number of times, a bit in the mask is set to indicate that the sub-block is likely to be accessed. When a block is evicted from the cache, the mask is also transferred for storage and only the sub-blocks identified by the mask as being likely to be accessed may be transferred for storage.

Abstract: A flash memory system includes a flash controller for controlling operation of at least two flash memory devices. A page buffer is allocated within each flash memory device, such that one page buffer functions as a designated target buffer and another page buffer functions as a mirror buffer. The flash controller transmits the page data to two flash memory devices simultaneously, such that no backup of the page data is required to be kept in the flash controller. Hence, there is no delay in writing the next page data from a host computer to the flash controller.