Abstract: Circuits, methods, and apparatus that adaptively control 1T and 2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having a number of address and control lines. The address and control lines of the redundant memory interface may be individually enabled and disabled. If a line in the additional interface is enabled, it and its corresponding line in the first interface drive a reduced load and may operate at the higher 1T data rate. If a line in the additional interface is disabled, then its corresponding line in the first interface drives a higher load and may operate at the slower 2T data rate. In either case, the operating speed of the interface may also be considered in determining whether each line operates with 1T or 2T timing.

Abstract: Where realtime performance-critical processing is executed in parallel with data integrity-critical processing, embodiments of the invention improve the realtime performance by raising the data transfer efficiency for sequential access-dominant realtime processing. In one embodiment, if a non-realtime processing command is received while read-ahead is in progress for a realtime processing command, processing of the non-realtime processing command is not started until a certain amount of data is cached. In addition, in order to prevent the periodicity disturbance of realtime processing, when the processing of the non-realtime processing command is postponed, the read-ahead is continued maximally until the timestamp at which the next realtime processing command is expected to be issued.

Abstract: Provided are a method, system, and program for destaging a track from cache to a storage device. The destaged track is retained in the cache. Verification is made of whether the storage device successfully completed writing data. Indication is made of destaged tracks eligible for removal from the cache that were destaged before the storage device is verified in response to verifying that the storage device is successfully completing the writing of data.

Abstract: Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative fills that are provided in response to source requests. The multi-processor system may comprise a first register file that retains register values associated with program instruction employing data from speculative fills, and a second register file that retains register values associated with data from speculative fills that have been determined to be coherent.

Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative data fills that are provided in response to source requests. The multi-processor system may comprise a first cache that retains cache data associated with program instructions employing data from speculative data fills, and a second cache that retains cache data associated with data from speculative data fills that have been determined to be coherent.

Abstract: A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units arid each memory unit has a unique corresponding address, the corresponding address using the binary system. The method includes making die corresponding address in a section with greater size smaller than the corresponding address in a section with smaller size, building a single bit-pattern for each section from all corresponding addresses, and comparing if at least one comparative bit of the given address matches those in any of the bit-patterns so as to determine the given address is located in one of the sections based on the comparison.

Abstract: While executing a command that accesses a sector on a disk-shaped recording medium placed in a data recording device, an address of a sector where it is difficult to read data is recorded in a memory. After that, a determination is made as to whether or not the data recording device is executing a command. If it is judged that the data recording device is not executing a command, the address of the sector is read from the memory, and then a bad sector is searched for by detecting whether or not it is difficult to read data from each of surrounding sectors adjacent to the sector, the address of which has been read.