Abstract: A flash memory is managed by reserving one or more cells as flag cells to represent the number N of bits to store in the cells of a memory block, selecting the value of N from at least three candidates, and programming the flag cell(s) to represent the selected value. A flash memory is managed by selecting a value of the number N>2 of bits to store in the cells of a portion (e.g. a block or page) of the memory, reserving one other cell of the memory as a flag cell to represent how many bits actually are stored in each cell of the portion, and, as the cells of the portion are successively programmed with 1?n?N bits, programming the flag cell to represent n.

Abstract: A flash memory that supports N>1-bit programming is managed by, for at least one block of the memory, selecting the value of N to use for the block, designating one or more cells of the block as flag cells, and programming the flag cells to represent the selected value of N. Preferably, N is encoded according to whether the threshold voltages of the flag cells are greater or less than a reference voltage common to all values of N. The other cells of the block then are programmed in accordance with the selected value of N. N and its flag cells are selected when the block is first used to store data. Subsequent to an erasure of the block, a different value of N may be selected.

Abstract: A method is disclosed that comprises creating a plurality of vaulting policies, each vaulting policy having one or more cycles specifying a movement of media to a destination location and a time to execute the cycle. The method further comprises associating a first vaulting policy of the plurality to a first set of media and associating a second vaulting policy of the plurality to a second set of media, the second set of media comprising a subset of the first set of media, the second vaulting policy superseding the first vaulting policy for the media contained in the subset.

Abstract: A physical extent assurance unit manages correspondence of a logical disk accessed from a host computer with physical extents. A data pattern generation response unit generates a predetermined data pattern, and returns this data pattern in response to a data request from the host computer. A pattern matching unit checks the data pattern of a storage area every access to storage media or periodically. When the entire area of the assured physical extent defines the predetermined data pattern, the pattern matching unit deleted the logical disk allocation of the assured physical extent.

Abstract: A speculative transfer mechanism transfers a source synchronous read request from a first clock domain to a second clock domain. The address portion having address information is transferred to the second clock domain in response to detecting a source synchronous address strobe latching signal. A pointer is generated in response to detecting the address strobe latching signal and passed into the second clock domain. In one embodiment, a pointer is retimed to be stable for a timing window for which a crossover of the address portion may be performed in the second clock domain. Request logic in the second clock domain generates a read command based on the address portion and the pointer.

Abstract: A device and method is provided for maintaining, upon unlocking of a memory, the lock status of the memory prior to the memory being unlocked and recreating the lock status when power is turned on again. An information storage device, such as a memory card, performs unlocking of a memory in response to a command input from an information processing apparatus and stores lock status data prior to the memory being unlocked in a non-volatile memory (NVM). When the information storage device is turned off and then on, the information storage device recreates a lock status of the memory on the basis of the lock status data stored in the storage means and performs memory access control based on the recreated lock status.

Abstract: Provided are a method, system, and program for destaging a track from cache to a storage device. The destaged track is retained in the cache. Verification is made of whether the storage device successfully completed writing data. Indication is made of destaged tracks eligible for removal from the cache that were destaged before the storage device is verified in response to verifying that the storage device is successfully completing the writing of data.

Abstract: A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.

Abstract: A storage system condition indicator and method provides a visual display representing the operating condition of a set of storage devices. Various operating conditions may be defined based on available storage capacity and capacity to store data redundantly. One or more indicators may be used to represent the operating condition of the set of storage devices. The indicator(s) may be used to indicate whether additional storage capacity is recommended and, in a storage array, which slot in the array should be updated with additional storage capacity.

Abstract: A dynamically expandable and contractible fault-tolerant storage system permits variously sized storage devices. Data is stored redundantly across one or more storage devices if possible. The layout of data across the one or more storage devices is automatically reconfigured as storage devices are added or removed in order to provide an appropriate level of redundancy for the data to the extent possible. A hash-based compression technique may be used to reduce storage consumption. Techniques for freeing unused storage blocks are also disclosed.

Abstract: A dynamically upgradeable fault-tolerant storage system permits a storage device to be replaced with a larger storage device. Data stored redundantly across multiple storage devices is reproduced on the replacement device, and the additional storage space on the replacement device is made available for redundantly storing additional data.

Abstract: Systems, methods, and device are provided for program stack handling. One method embodiment includes recognizing that a fault has occurred because a particular address range in a memory stack has been accessed. The method includes evaluating a current utilized size of regions in the memory stack. A particular address range between the current utilized size of regions in the memory stack is then relocated.

Abstract: An address translator capable of reducing system loads in address translation and an overhead in switching between operating systems. A plurality of address translation buffers classifies and stores virtual addresses and real addresses based on a plurality of operating systems which is run by a processor. For example, the address translation buffers store the virtual addresses and the real addresses in correspondence with the operating systems. According to a running operating system, an address translation controller accesses a corresponding address translation buffer to translate virtual addresses to real addresses.

Abstract: In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.

Abstract: An instruction set is executed from Read Only Memory (ROM). When a current instruction in the instruction set corresponds to a reserved patch memory block of ROM, a Random Access Memory (RAM) index and a ROM return address are loaded into a memory map, and a program counter is set to a first reserved ROM address. After jumping the program counter to the first reserved ROM address, the program counter is jumped to RAM based on the RAM index to execute a patch code, which includes at least one instruction to set the program counter to a second reserved ROM address. When the program counter equals the second reserved ROM address, the ROM return address is retrieved. Then the instruction set is executed from ROM based on the ROM return address.

Abstract: A flash memory is managed by reserving one or more cells as flag cells to represent the number N of bits to store in the cells of a memory block, selecting the value of N from at least three candidates, and programming the flag cell(s) to represent the selected value. A flash memory is managed by selecting a value of the number N>2 of bits to store in the cells of a portion (e.g. a block or page) of the memory, reserving one other cell of the memory as a flag cell to represent how many bits actually are stored in each cell of the portion, and, as the cells of the portion are successively programmed with 1?n?N bits, programming the flag cell to represent n.

Abstract: The system according to the present invention comprises a first storage area for storing a plurality of logical volume data where the attributes on a plurality of logical volumes are recorded respectively, a second storage area for storing allocation destination candidate data where the attributes on an allocation destination candidate selected from one or more allocation destination candidates are recorded, a third storage area for storing one or more history data to indicate a relationship of a logical volume having a certain attribute among the plurality of logical volumes to an allocation destination candidate having a certain attribute among one or more allocation destination candidates, a device refining unit for refining the plurality of logical volume data to one or more logical volume data based on the plurality of logical volume data, allocation destination candidate data, and one or more history data, and a refined result output section for outputting the content of the refined one or more logical

Abstract: An object of the present invention is to provide a storage controller capable of facilitating extension of storage capacity while suppressing investment related to storage capacity.

Abstract: A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units and each memory unit has a unique corresponding address, the corresponding address using the binary system. The method includes making the corresponding address in a section with greater size smaller than the corresponding address in a section with smaller size, building a single bit-pattern for each section from all corresponding addresses, and comparing if at least one comparative bit of the given address matches those in any of the bit-patterns so as to determine the given address is located in one of the sections based on the comparison.

Abstract: With the migration of a logical volume between virtualization apparatuses, there has been a need to change the setting of a host computer in order to access a migration destination logical volume. In a control method for a computer system including a host computer, one or more storage systems, and plural virtualization apparatuses, a first virtualization apparatus includes a first memory and manages a first logical volume to which the host computer issues an access request, and a second virtualization apparatus includes a second memory and manages a second logical volume to which the host computer issues an access request, wherein the control method associates a first real storage area on the storage system, which has been associated with the first logical volume, with the second logical volume, and stores, in the second memory, first identification information that uniquely identifies the first logical volume within the computer system.