Abstract: The present application provides a method for preparing a memory device.

Abstract: A semiconductor substrate including a first main surface and a second main surface opposing each other is provided. The semiconductor substrate includes a first semiconductor region of a first conductivity type. The semiconductor substrate includes a plurality of planned regions where a plurality of second semiconductor regions of a second conductivity type forming pn junctions with the first semiconductor region are going to be formed, in a side of the second main surface. A textured region is formed on surfaces included in the plurality of planned regions, in the second main surface. The plurality of second semiconductor regions are formed in the plurality of planned regions after forming the textured region. The first main surface is a light incident surface of the semiconductor substrate.

Abstract: A manufacturing method of a semiconductor structure including the following steps is provided: forming a first metal layer on a substrate; forming an insulating layer on the first metal layer; forming an oxide semiconductor material layer on the insulating layer; performing an annealing treatment to the oxide semiconductor material layer; forming an etch stopping material layer on the oxide semiconductor material layer; forming a photoresist material layer on the etch stopping material layer and defining thereof with a half tone photomask to form a photoresist pattern; using the photoresist pattern as a mask, patterning the etch stopping material layer to form an etch stopping pattern, and patterning the oxide semiconductor material layer to form an oxide semiconductor layer; removing the photoresist pattern; using the etch stopping pattern as the mask, patterning the insulating layer; forming a second metal layer on the etch stopping pattern; and patterning the oxide semiconductor layer.

Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a n-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.

Abstract: A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.

Abstract: An imaging element includes a photoelectric conversion unit formed by laminating a first electrode 21, a photoelectric conversion layer 23A, and a second electrode 22. Between the first electrode 21 and the photoelectric conversion layer 23A, a first semiconductor material layer 23B1 and a second semiconductor material layer 23B2 are formed from the first electrode side, and the second semiconductor material layer 23B2 is in contact with the photoelectric conversion layer 23A. The photoelectric conversion unit further includes an insulating layer 82 and a charge accumulation electrode 24 disposed apart from the first electrode 21 so as to face the first semiconductor material layer 23B1 via the insulating layer 82. When the carrier mobility of the first semiconductor material layer 23B1 is represented by ?1, and the carrier mobility of the second semiconductor material layer 23B2 is represented by ?2, ?2<?1 is satisfied.

Abstract: A method includes capturing an image of a wafer, the wafer comprising a first conductive contact over an active region of the wafer and a second conductive contact over a shallow trench isolation (STI) region abutting the active region; identifying a brightness of a first contact region in the captured image at which the first conductive contact is rendered; identifying a brightness of a second contact region in the captured image at which the second conductive contact is rendered; and in response to the identified brightness of the first contact region in the captured image being substantially the same as the identified brightness of the second contact region in the captured image, determining that the second conductive contact is shorted to the first conductive contact.

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

Abstract: A magnetic memory according to an embodiment includes: a magnetic member including a first to third magnetic parts, the first magnetic part including a first portion and a second portion and extending in a first direction from the first portion to the second portion, the second magnetic part extending in a second direction that crosses the first direction, and the third magnetic part connecting the second magnetic part and the first portion; a first nonmagnetic metal layer arranged along the third magnetic part, the first nonmagnetic metal layer including a first end portion on a side of the second portion, a position of the first end portion along the first direction being between positions of the first and second portions along the first direction; and a first and second electrodes supplying a current between the first and second magnetic parts via the third magnetic part.

Abstract: A method used in forming integrated circuitry comprises forming a plurality of conductive vias comprising conductive material. The conductive vias are spaced relative one another by intermediate material. A discontinuous material is formed atop the conductive material of the vias and atop the intermediate material that is between the vias. Metal material is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the vias. The metal material with discontinuous material there-below is formed to comprise a conductive line that is atop the intermediate material that is between the vias and is directly against individual of the vias. Structures independent of method are disclosed.

Abstract: A semiconductor package device includes a leadframe, a first die and a package body. The leadframe includes a first die paddle and a lead. The first die paddle has a first surface and a second surface opposite to the first surface. The first die is disposed on the first surface of the first die paddle. The package body covers the first die and at least a portion of the first surface of the first die paddle and exposing the lead. The package body has a first surface and a second surface opposite to the first surface. The second surface of the package body is substantially coplanar with the second surface of the first die paddle. The lead extends from the second surface of the package body toward the first surface of the package body. A length of the lead is greater than a thickness of the package body.

Abstract: An integrated circuit structure includes a first material block comprising a first block insulator layer and a first multilayer stack on the first block insulator layer, the first multilayer stack comprising interleaved pillar electrodes and insulator layers. A second material block is stacked on the first material block and comprises a second block insulator layer, and a second multilayer stack on the second block insulator layer, the second multilayer stack comprising interleaved pillar electrodes and insulator layers. At least one pillar extends through the first material block and the second material block, wherein the at least one pillar has a top width at a top of the first and second material blocks that is greater than a bottom width at a bottom of the first and second material blocks.

Abstract: The present disclosure generally relates to display technologies, and in particular, to a display motherboard, and a method of fabricating the display motherboard. A display motherboard includes a plurality of display substrate units on a base substrate, a gap between adjacent display substrate units, and at least one electrostatic equilibrator in the gap. Each display substrate unit includes at least one trace comprising a display portion that extends into the display substrate unit and a gap portion that extends into a gap adjacent to the display substrate unit. Each electrostatic equilibrator is configured to electrically couple gap portions of traces of the adjacent display substrate units, so as to form a conductive path between the gap portions.

Abstract: An inductor conductor design which minimizes the impact of skin effect in the conductors at high frequencies in integrated circuits and the method of manufacture thereof is described herein.

Abstract: The semiconductor device that supplies a charging current to a bootstrap capacitor includes a semiconductor layer, an N+-type diffusion region, an N-type diffusion region, a P+-type diffusion region, a P-type diffusion region, an N+-type diffusion region, a source electrode, a drain electrode, a back gate electrode, and a gate electrode. The N+-type diffusion region and the N-type diffusion region are electrically connected to a first electrode of the bootstrap capacitor. The N+-type diffusion region is supplied with a power supply voltage. The source electrode is connected to the N+-type diffusion region and is supplied with the power supply voltage. The back gate electrode is connected to a region separated from the N+-type diffusion region and is grounded. The breakdown voltage between the source electrode and the back gate electrode is greater than the power supply voltage.

Abstract: A photodetector array (1) is provided comprising a plurality of pixels (10ij) between a supply line (4j) and a common electrode (2). Respective pixels (10ij) comprise a photon radiation sensitive element (11ij) arranged in a series connection with a switching element (20ij) characterized in that the series connection further includes a resistive element (30ij).

Abstract: A display panel, a manufacturing method thereof and a display device are provided. The display panel includes a substrate and a plurality of active switches disposed on the substrate. The active switch includes a gate layer disposed on a bottom portion. The gate layer is wound with an insulation medium layer, and the insulation medium layer includes a light-obstructing layer disposed on a side portion of the gate layer.

Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.

Abstract: Disclosed is a complementary metal oxide semiconductor (CMOS) image sensor. The image sensor comprises a first separation zone in a substrate, the first separation zone defining first and second pixel regions arranged in a first direction, the first separation zone including first parts substantially parallel extending in the first direction, and the substrate including a first active region vertically overlapping one of the first parts and a second active region vertically overlapping another of the first parts. The image sensor further comprises first and second photoelectric conversion devices arranged in the first direction on at least one of the first and second pixel regions in the substrate, and a source follower gate on the first active region of the substrate.

Abstract: The present application provides a display panel and an electronic device. The display panel includes a control circuit, a light emitting layer, a color film layer, and a cover plate, wherein the color film layer is disposed between the light emitting layer and the cover plate, and the color film layer comprises a photosensitive region comprising a plurality of color film units and a plurality of photosensors which are spaced apart. Wherein, a first light shielding film is disposed on surfaces of the plurality of photosensors facing the light emitting layer.