Patents Examined by Sara Crane
  • Patent number: 7863200
    Abstract: A process to encapsulate electronic modules in a manner which is substantially resistant to water diffusion yet is carried out at moderate temperatures below 300° C., preferably below 150° C. is provided. The process forms a housing for electronic modules, in particular sensors, integrated circuits and optoelectronic components. The process includes the steps of: providing a substrate, of which at least a first substrate side is to be encapsulated; providing a vapor-deposition glass source; arranging the first substrate side in such a manner with respect to the vapor-deposition glass source that the first substrate side can be vapor-coated; and vapor-coating the first substrate side with a glass layer.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: January 4, 2011
    Assignee: Schott AG
    Inventors: Jürgen Leib, Dietrich Mund
  • Patent number: 7531379
    Abstract: A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor may be formed entirely over a field oxide region of the CMOS imager, entirely over an active area of a pixel sensor cell, or partially over a field oxide region and partially over an active pixel area of a pixel sensor cell.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: May 12, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Howard Rhodes, Jeff Mckee
  • Patent number: 7429495
    Abstract: A system and method for manufacturing micro cavities at the wafer level using a unique, innovative MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed, with epoxy bonded single-crystalline silicon membrane as cap and deposited and/or electroplated metal as sidewall, on substrate wafers. The epoxy is also the sacrificial layer. It is removed from within the cavity through small etch access holes etched in the silicon cap before the etch access holes are sealed under vacuum. The micro cavities manufactured therein can be used as pressure sensors or for packaging MEMS devices under vacuum or inert environment. In addition, the silicon membrane manufactured therein can be used to manufacture RF switches.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: September 30, 2008
    Inventor: Chang-Feng Wan
  • Patent number: 7345300
    Abstract: The invention relates to a light emitting component with organic layers and emission of triplet exciton states (phosphorescent light) with increased efficiency, having a layer sequence with a hole injecting contact (anode), one or more hole injecting and transporting layers, a system of layers in the light emission zone, one or more electron transport and injection layers and an electron injecting contact (cathode), characterized in that the light emitting zone comprises a series of heterojunctions with the materials A and B (ABAB . . . ) that form interfaces of the type “staggered type II”, one material (A), having hole transporting or bipolar transport properties and the other material (B) having electron transporting or bi-polar transport properties, and at least one of the two materials A or B being mixed with a triplet emitter dopant that is able to efficiently convert its triplet exciton energy into light.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: March 18, 2008
    Inventors: Dashan Qin, Jan Blochwitz-Nimoth, Xiang Zhou, Martin Pfeiffer
  • Patent number: 7339246
    Abstract: The invention relates to a large-area sensor arrangement, notably a flat dynamic X-ray detector (FDXD). The light-sensitive and/or X-ray-sensitive sensors (pixels) of the sensor arrangement are arranged in a planar distribution on a substrate (1), thus forming a sensitive layer (20). On the top surface of the layer (20) there is provided a contact point (23) for each sensor, which contact point is connected to an integrated circuit (6) via one or more connection layers (30, 40). A multi-layer, very compact construction is thus obtained in which the electronic evaluation circuitry (6) is arranged in a planar fashion and parallel to the sensors (20). Preferably, a respective evaluation circuit in the circuit (6) is associated with each sensor, resulting in very short paths and also in a reduction of noise.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: March 4, 2008
    Assignee: Koninklijke Philips Electronics, N.V.
    Inventors: Augusto Nascetti, Michael Overdick
  • Patent number: 7315044
    Abstract: A thin film transistor (TFT) array panel includes: an insulating substrate (110); first and second semiconductor members (151 a,b) formed on the substrate and having opposite conductivity; a first gate member (121a) formed on a first layer (140), insulated from the first and the second semiconductor members and overlapping one of the first and the second semiconductor members; a second gate member (122a) formed on the first layer (140), separated from the first gate member, and insulated from the first and the second semiconductor members (151 a,b), the second gate member (122a) not overlapping the first and the second semiconductor members; a first data member (162) formed on a second layer (160), connected to one of the first and the second semiconductor members (151 a,b) and insulated from the first (121a) and the second (122a) gate members; and a first connection (123) formed on the second layer (160) and connecting the first gate member (121a) and the second gate member (122a).
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: January 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Won Hwang, Woo-Suk Chung
  • Patent number: 7315075
    Abstract: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: January 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: John M Aitken, Ethan H. Cannon, Philip J. Oldiges, Alvin W. Strong
  • Patent number: 7312485
    Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100> direction. Additionally, longitudinal tensile stress is applied to the channels.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: December 25, 2007
    Assignee: Intel Corporation
    Inventors: Mark Armstrong, Gerhard Schrom, Sunit Tyagi, Paul A. Packan, Kelin J. Kuhn, Scott Thompson
  • Patent number: 7312474
    Abstract: A light emitting diode is provided having a Group III nitride based superlattice and a Group III nitride based active region on the superlattice. The active region has at least one quantum well structure. The quantum well structure includes a first Group III nitride based barrier layer, a Group III nitride based quantum well layer on the first barrier layer and a second Group III nitride based barrier layer. A Group III nitride based semiconductor device and methods of fabricating a Group III nitride based semiconductor device having an active region comprising at least one quantum well structure are provided. The quantum well structure includes a well support layer comprising a Group III nitride, a quantum well layer comprising a Group III nitride on the well support layer and a cap layer comprising a Group III nitride on the quantum well layer.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: December 25, 2007
    Assignee: Cree, Inc.
    Inventors: David Todd Emerson, James Ibbetson, Michael John Bergmann, Kathleen Marie Doverspike, Michael John O'Loughlin, Howard Dean Nordby, Jr., Amber Christine Abare
  • Patent number: 7309898
    Abstract: A method and apparatus for improving the latchup tolerance of circuits embedded in an integrated circuit while avoiding the introduction of noise from such tolerance into the power rails.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: December 18, 2007
    Assignee: International Business Machines Corporation
    Inventors: Raminderpal Singh, Steven Howard Voldman
  • Patent number: 7309922
    Abstract: In a lower substrate, a display apparatus having the lower substrate and a method of manufacturing the lower substrate, the lower substrate includes a pixel area and a circuit area. An image is displayed in the pixel area. A first signal electrode is disposed in a circuit area. A first insulating layer includes an opening, through which the first signal electrode is exposed. A second signal electrode is disposed on the first insulating layer in the circuit area, and spaced apart from the first signal electrode. A second insulating layer is disposed on the first insulating layer, and includes a contact hole, through which the first and second signal electrodes are exposed. A conductive layer electrically connects the first signal electrode to the second signal electrode. Therefore, a manufacturing process is simplified so that a yield of the lower substrate is increased.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: December 18, 2007
    Assignee: Samsun Electronics Co., Ltd.
    Inventors: Hyun-Young Kim, Joo-Sun Yoon, Bong-Ju Kim, Seung-Gyu Tae
  • Patent number: 7307008
    Abstract: Methods of forming a cell pad contact hole on an integrated circuit include forming adjacent gates on an integrated circuit substrate having a source/drain region extending between the gates. Gate spacers are formed on facing sidewalls of the adjacent gates. A cell pad contact hole is formed aligned to the gates and gate spacers that exposes the source/drain region in the integrated circuit substrate. A first poly film is formed in the cell pad contact hole. An ion region is formed in the source/drain region by ion-implanting through the first poly film and a second poly film is formed on the first poly film that substantially fills the cell pad contact hole.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: December 11, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Chul Oh, Gyo-Young Jin
  • Patent number: 7307317
    Abstract: The invention provides a semiconductor device which consumes less power in pending. The invention further provides a semiconductor device in which a gate electrode is provided over both sides of a semiconductor thin film which forms a transistor, a logic signal is applied to a first gate electrode, a threshold value control signal is applied to a second gate electrode, and a threshold value of a transistor which forms the semiconductor device is controlled by a potential of the second gate electrode, and a driving method thereof. Then, the invention provides a semiconductor device provided with a plurality of logic circuits formed of such a transistor with a back gate and a driving method thereof.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: December 11, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 7307318
    Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: December 11, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Yuuichi Hirano, Takashi Ipposhi
  • Patent number: 7304324
    Abstract: An example memory includes an address control portion, a protection film, a property deterioration material layer, data storage areas, and bonding pads. The protection film protects an organic semiconductor layer of a semiconductor circuit and prevents intrusion of moisture or chemical molecules in the air, light, or the like, into the organic semiconductor layer. Deterioration of the organic semiconductor layer is started by breaking the protection film and using a specified means, thus starting operation of the lifetime period. The property deterioration material layer contains a material for deteriorating the property of the organic semiconductor and deterioration of the organic semiconductor layer is started, for example, by diffusing the material into the organic semiconductor layer.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: December 4, 2007
    Assignee: Pioneer Corporation
    Inventors: Kazuo Kuroda, Shuuichi Yanagisawa
  • Patent number: 7301184
    Abstract: Shift register electrodes are formed in an imaging area and a peripheral area through use of a single layer of conductive film, and a thick insulating film is deposited over those electrodes and planarized. The thick insulating film overlying the shift register electrodes in the peripheral area is kept as it is and on the other hand, the thick insulating film overlying the shift register electrodes is etched to just fill gaps between the shift register electrodes with the film, thereby allowing a light shielding metal layer overlying the shift register electrodes in the peripheral area and insulating films sandwiched therebetween to be formed without discontinuity. Since metal interconnect lines in the peripheral area have a thick and planarized insulating film formed thereunder, parasitic capacitance between diffusion layers/electrodes and the metal interconnect lines can be reduced, leading to reduction in power consumption of image sensor.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: November 27, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Toru Kawasaki
  • Patent number: 7297990
    Abstract: A silicon-based interband tunneling diode (10, 110) includes a degenerate p-type doping (22, 130) of acceptors, a degenerate n-type doping (32, 118) of donors disposed on a first side of the degenerate p-type doping (22, 130), and a barrier silicon-germanium layer (20, 136) disposed on a second side of the degenerate p-type doping (22, 130) opposite the first side. The barrier silicon-germanium layer (20, 136) suppresses diffusion of acceptors away from a p/n junction defined by the degenerate p-type and n-type dopings (22, 32, 118, 130).
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: November 20, 2007
    Assignee: The Ohio State University
    Inventors: Paul R. Berger, Phillip E. Thompson, Niu Jin
  • Patent number: 7294859
    Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: November 13, 2007
    Assignee: Cree, Inc.
    Inventors: Davis Andrew McClure, Alexander Suvorov, John Adam Edmond, David Beardsley Slater, Jr.
  • Patent number: 7294901
    Abstract: A p impurity region (3) defines a RESURF isolation region in an n? semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n? semiconductor layer (2) in the RESURF isolation region. An nMOS transistor (103) is provided in the trench isolation region. A control circuit is provided in the RESURF isolation region excluding the trench isolation region. An n+ buried impurity region (4) is provided at the interface between the n? semiconductor layer (2) and a p? semiconductor substrate (1), and under an n+ impurity region 7 connected to a drain electrode (14) of the nMOS transistor (103).
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: November 13, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazuhiro Shimizu
  • Patent number: 7294936
    Abstract: In the case where a first semiconductor chip 100 and a second semiconductor chip 200 are stacked, both the semiconductor chips 100 and 200 are connected using micro bumps, in which a circuit block in the first semiconductor chip and a circuit block in the second semiconductor chip are connected by the micro bumps, and the circuit block in the second semiconductor chip is also connected to the external electrode by the micro bumps through the first semiconductor chip. Further, micro bumps 121, 221 that connect circuit blocks 101, 102, 103, 104 and 210 of both the semiconductor chips 100, 200 and the micro bumps 122, 222 that connect the circuit block 210 in one chip 200 to an external electrode are arranged in different positions.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: November 13, 2007
    Assignee: Sony Corporation
    Inventor: Kazuhiro Kondo