Abstract: In the case where a first semiconductor chip 100 and a second semiconductor chip 200 are stacked, both the semiconductor chips 100 and 200 are connected using micro bumps, in which a circuit block in the first semiconductor chip and a circuit block in the second semiconductor chip are connected by the micro bumps, and the circuit block in the second semiconductor chip is also connected to the external electrode by the micro bumps through the first semiconductor chip. Further, micro bumps 121, 221 that connect circuit blocks 101, 102, 103, 104 and 210 of both the semiconductor chips 100, 200 and the micro bumps 122, 222 that connect the circuit block 210 in one chip 200 to an external electrode are arranged in different positions.

Abstract: Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.

Abstract: A NTCDA single crystal is used as a photoelectric current multiplier layer, and Au thin films are formed as electrodes on the opposite surfaces of the multiplier layer by a vapor deposition method to form a sandwich type cell. When a voltage is applied to the NTCDA single crystal by the electrodes from a dc power source and a monochromatic light is applied, a multiplied photoelectric current flows between the electrodes. A rise of this element at light-on is considerably faster than when a vapor-deposited layer is used as a photoelectric current multiplier layer to permit a faster response.

Abstract: A micro-lens built-in vertical cavity surface emitting laser (VCSEL) includes a substrate and a lower reflector formed on the substrate. An active layer is formed on the lower reflector, generating light by a recombination of electrons and holes. An upper reflector is formed on the active layer including a lower reflectivity than that of the lower reflector. A micro-lens is disposed in a window region through which the laser beam is emitted. A lens layer is formed on the upper reflector with a transparent material transmitting a laser beam; the lens layer includes the micro-lens. An upper electrode is formed above the upper reflector excluding the window region a lower electrode formed underneath the substrate.

Abstract: In a conventional semiconductor device, there is a problem that an N-type diffusion region provided for protecting an element from an overvoltage is narrow and a breakdown current is concentrated so that a PN junction region for protection is broken. In a semiconductor device of the present invention, an N-type buried diffusion layer is formed across a substrate and an epitaxial layer. A P-type buried diffusion layer is formed across a wider region on an upper surface of the N-type buried diffusion layer so that a PN junction region for overvoltage protection is formed. A P-type diffusion layer is formed so as to be connected to the P-type diffusion layer. A breakdown voltage of the PN junction region is lower than a breakdown voltage between a source and a drain. With this structure, the concentration of the breakdown current is prevented so that the semiconductor device can be protected from the overvoltage.

Abstract: In layer structure 20 of a semiconductor laser of a surface emitting type, 21 and 24 represent an n-type contact layer made of n-type GaN and a p-layer made of p-type AlGaN, respectively. In the laser, an n-type DBR layer 22 made of n-type InGaN and a DBR layer 25 made of dielectric are formed on and below a InGaN active layer 23, respectively, each of which forms a reflection surface vertical to the z axis. By forming a reflection surface vertical to the z axis at each of on and above the active layer 23, a resonator is obtained. Here optical distance between two reflection facets are arranged to an integral multiple of half a oscillation wavelength. Consequently, the present invention enables to produce a semiconductor laser of a surface emitting type easier by far compared with a conventional invention.

Abstract: The present invention relates to a chip package that includes a semiconductor device and at least one micro electromechanical structure (MEMS) such that the semiconductor device and the MEMS form an integrated package. One embodiment of the present invention includes a semiconductor device, a first MEMS device disposed in a conveyance such as a film, and a second MEMS device disposed upon the semiconductor device through a via in the conveyance. The present invention also relates to a process of forming a chip package that includes providing a conveyance such as a tape automated bonding (TAB) structure, that may hold at least one MEMS device. The method is further carried out by disposing the conveyance over the active surface of the device in a manner that causes the at least one MEMS to communicate electrically to the active surface. Where appropriate, a sealing structure such as a solder ring may be used to protect the MEMS.

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (104) is integrated at the top metal interconnect level (104) and may be implemented with only one additional masking layer. The decoupling capacitor (106) is formed on a copper interconnect line (104a). An aluminum cap layer (118) provides electrical connection to the top electrode (112) of the decoupling capacitor (106).

Abstract: An improved integrated optical device (5a-5g) is disclosed containing first and second devices (10a-10g; 15a, 15e), optically coupled to each other and formed in first and second different material systems. One of the first or second devices (10a-10g, 15a, 15e) has a Quantum Well Intermixed (QWI) region (20a, 20g) at or adjacent a coupling region between the first and second devices (10a-10g; 15a, 15e). The first material system may be a III-V semiconductor based on Gallium Arsenide (GaAs) or Indium Phosphide (InP), while the second material may be Silica (SiO2), Silicon (Si), Lithium Niobate (LiNbO3), a polymer, or glass.

Abstract: A light emitting layer forming section (8) including an n-type conductivity type clad layer (2), an active layer (3) and p-type conductivity type clad layers (4) and (6) is laminated on a semiconductor substrate (1), and further, a contact layer (9) made of a material having substantially the same lattice constant and thermal expansion coefficient as those of the semiconductor substrate is laminated on the light emitting layer forming section. The light emitting layer forming section and the contact layer are formed in such a manner as to satisfy the following inequality: 1.5?(d1/d2)?2.8, where d1 represents the thickness of the contact layer, and d2 represents the thickness of the light emitting layer forming section. As a consequence, it is possible to provide a semiconductor laser for a high output, in which a COD level can become high and a lifetime can be prolonged even if the light emitting layer forming section is as thick as 4 ?m or more.

Abstract: A semiconductor device has trenches for defining active regions. After a thin diffusion barrier is deposited in the trenches, some of the trenches are selectively etched to leave different areas in the trench. One of the areas has the diffusion barrier completely removed so that the underlying layer is exposed. Another area has the diffusion barrier remaining. An oxidation step follows so that oxidation occurs at a corner where the diffusion barrier was removed whereas the oxidation is blocked by the diffusion barrier, which functions as a barrier to oxygen. The corners for oxidation are those in which compressive stress is desirable, such as along a portion of the border of a P channel transistor. The corners where the diffusion barrier is left are those in which a compressive stress is undesirable such as the border of an N channel transistor.

Abstract: Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A first stress layer has a first thickness and is configured to impart a first determined stress to the first portion of the plurality of field effect transistors. A second stress layer has a second thickness and is configured to impart a second determined stress to the second portion of the plurality of field effect transistors.

Abstract: Semiconductor memory devices are provided that comprise unit memory cells. The unit memory cells include a first planar transistor in a semiconductor substrate, a vertical transistor disposed on the first planar transistor and a second planar transistor in series with the first planar transistor. The first planar transistor and the second planar transistor may have different threshold voltages. The semiconductor memory device may further include word lines. One of these word lines may form the gate of the second planar transistor a unit memory cell.

Abstract: A unit pixel for use in a CMOS image sensor is employed to minimize a contact resistance between adjacent unit pixels by employing a supplementary p-well or modifying a unit pixel layout. The unit pixel having a photodiode, a transfer transistor, a reset transistor, a drive transistor and a selection transistor, the unit pixel including: a first active area having a protrusive portion thereof where the transfer transistor, the reset transistor and a VDD contact are formed, in which the VDD contact is formed apart from the photodiode in an adjacent unit pixel by a predetermined distance, to thereby minimize a leakage current, the first active area being connected to the photodiode; and a second active area where the drive transistor, the selection transistor and an output contact are formed, wherein the second active area is perpendicularly connected to the first active area.

Abstract: Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.

Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.

Abstract: A III-nitride electronic device structure including doped material, an active region and a barrier material arranged to suppress transport of dopant from the doped material into the active region, wherein the barrier material comprises high-Al content AlxGayN, wherein x+y=1, and x?0.50. In a specific aspect, AIN is used as a migration/diffusion barrier layer at a thickness of from about 5 to about 200 Angstroms, to suppress flux of magnesium and/or silicon dopant material into the active region of the III-nitride electronic device, e.g., a UV LED optoelectronic device.

Abstract: Symmetric quantum dots are embedded in quantum wells. The symmetry is achieved by using slightly off-axis substrates and/or overpressure during the quantum dot growth. The quantum dot structure can be used in a variety of applications, including semiconductor lasers.

Abstract: A multilayer interconnection structure that offers a fast semiconductor operation is realized by employing copper wiring, electro migration of which is prevented from occurring by providing a via plug that includes a layer of a high melting-point metal, such as tungsten.

Abstract: Methods of packaging a semiconductor light emitting device positioned in a reflective cavity are provided. A first quantity of encapsulant material is dispensed into the reflective cavity including the light emitting device therein and the first quantity of encapsulant in the reflective cavity is cured. A second quantity of encapsulant material is dispensed onto the cured first quantity of encapsulant material. A lens is positioned in the reflective cavity on the dispensed second quantity of encapsulant material. The dispensed second quantity of encapsulant material is cured to attach the lens in the reflective cavity.