Patents Examined by Sara W. Crane
  • Patent number: 7683435
    Abstract: This disclosure relates to misalignment-tolerant multiplexing/demultiplexing architectures. One architecture enables communication with a conductive-structure array having a narrow spacing and pitch. Another architecture can comprise address elements having a width substantially identical to that of conductive-structures with which each of these address elements is capable of communicating. Another architecture can comprise rows of co-parallel address elements oriented obliquely relative to address lines and/or conductive structures.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: March 23, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Xiaofeng Yang, Sriram Ramamoorthi, Galen H. Kawamoto
  • Patent number: 7217948
    Abstract: The present invention relates to a preferred semiconductor substrate for the production of devices. The semiconductor substrate is comprised of GaAs. Then, a plurality of quantum rings, which are composed of GaSb and have a substantially elliptical shape with an aspect ratio of 2 or more but 5 or less, are formed on a surface of the semiconductor substrate. These quantum rings extend along in the substantially same direction. In a case where a light beam is irradiated onto the surface of the semiconductor substrate, among the polarized components of the irradiated light, one polarized component parallel to the long-axis direction of the ellipse that is an extending direction of each quantum ring is reflected, while another polarized component parallel to the short-axis direction thereof is transmitted. That is, the semiconductor substrate reflects one polarized component, and transmits the other polarized component.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: May 15, 2007
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Tadataka Edamura
  • Patent number: 6998649
    Abstract: A semiconductor light-emitting device capable of attaining a surface plasmon effect while attaining excellent ohmic contact is provided. This semiconductor light-emitting device comprises a semiconductor layer formed on an emission layer, a first electrode layer formed on the semiconductor layer and a second electrode layer, formed on the first electrode layer, having a periodic structure. The first electrode layer is superior to the second electrode layer in ohmic contact with respect to the semiconductor layer, and the second electrode layer contains a metal exhibiting a higher plasma frequency than the first electrode layer.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: February 14, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Masayuki Hata
  • Patent number: 6803604
    Abstract: An integrated semiconductor optical-emitting device includes a surface-emission laser diode and an EA-type semiconductor optical modulator integrated commonly on a GaAs substrate in a direction perpendicular to the GaAs substrate.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: October 12, 2004
    Assignee: Ricoh Company, Ltd.
    Inventors: Takashi Takahashi, Shunichi Sato
  • Patent number: 6744065
    Abstract: A single electron tunnelling device is formed by positioning between first and second electrodes a particle formed of a material having a first conductivity characteristic having a surface layer of a material of a second conductivity characteristic, the thickness of said layer being sufficiently small to support quantum mechanical tunnelling therethrough.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: June 1, 2004
    Assignee: BTG International Limited
    Inventors: Lars Ivar Samuelson, Knut Wilfried Deppert
  • Patent number: 6407405
    Abstract: A method of growing p-type group II-VI compound semiconductor crystals, includes a step of forming ZnO layers and ZnTe layers alternately on a ZnO substrate, the ZnO layer being not doped with impurities and having a predetermined impurity concentration, and the ZnTe layer being doped with p-type impurities N to a predetermined impurity concentration or higher.
    Type: Grant
    Filed: May 18, 2000
    Date of Patent: June 18, 2002
    Assignees: Stanley Electric Co., Ltd.
    Inventors: Michihiro Sano, Takafumi Yao
  • Patent number: 6046476
    Abstract: In an input protection circuit having an SOI structure for protecting a MOSFET against breaking caused by a high voltage such as static electricity, a trench is provided in an SOI substrate to vertically pass through a silicon layer and a buried oxide film and reach the interior of a P-type silicon substrate. An n.sup.+ polysilicon layer is buried in the trench, to be connected with the silicon substrate by a P-N junction. A wire is connected to the n.sup.+ polysilicon layer. An end of the wire is connected to an input pad, and another end thereof is connected to an internal circuit. An input voltage is limited by an avalanche breakdown at the P-N junction in the interface between the n.sup.+ polysilicon layer and the P-type silicon substrate.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: April 4, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fukashi Morishita, Kazutami Arimoto
  • Patent number: 5894157
    Abstract: A method for fabricating a MOS transistor having an offset resistance in a channel region controlled by a gate voltage and structure thereof is disclosed. A gate electrode is divided into three adjacent regions of respectively a second conductivity type, first conductivity type and second conductivity type connected laterally to one another on a channel region. A gate control voltage is applied to a central region of the first conductivity type, and a predetermined voltage between maximum and minimum values of the gate control voltage is applied to left and right adjacent regions of the second conductivity type. If a gate turn-on voltage is applied to the central region the gate turn-on voltage is forward biased to the adjacent left and right regions and is therefore also applied to the forwardly biased left and right regions. The effective length of the gate electrode then becomes the total length of the central region and the left and right adjacent regions.
    Type: Grant
    Filed: June 27, 1994
    Date of Patent: April 13, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Koo Han, Byung-Hyuk Min
  • Patent number: 5877478
    Abstract: A semiconductor substrate made of silicon or the like and having an active region is used as part of a package. Bumps are formed on a major surface of the semiconductor substrate. One end of each lead is connected to a corresponding bump, and the other end of the lead is located outside the major surface of the semiconductor substrate. An adhesive such as a thermoplastic resin is applied to the major surface of the semiconductor substrate. An upper substrate is located on the adhesive. The upper substrate is made of a metal plate, an insulating plate, or a semiconductor substrate. The upper substrate covers at least the active region of the semiconductor substrate, the bumps, and the lead portions on the semiconductor substrate.
    Type: Grant
    Filed: September 12, 1994
    Date of Patent: March 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomoyuki Ando
  • Patent number: 5874750
    Abstract: A pressure-contact type semiconductor device such as an insulated gate bipolar transistor. The device includes semiconductor chip, a gate electrode on a first surface of the semiconductor chip, an emitter electrode insulated and separated from the gate electrode, and an emitter sensing electrode on the first surface of the semiconductor chip. A collector layer is on the second surface of the semiconductor chip. The emitter sensing electrode monitors the emitter voltage. Because the emitter sensing electrode is on the semiconductor chip, the emitter sensing electrode is not influenced by inductance between an emitter and an emitter terminal.
    Type: Grant
    Filed: November 6, 1996
    Date of Patent: February 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Yanagisawa, Michiaki Hiyoshi
  • Patent number: 5866930
    Abstract: A semiconductor device comprises a first conducting layer, a first insulating layer formed on the first conducting layer, a second conducting layer formed on the first insulating layer and facing the first conducting layer, wherein, at least part of a peripheral portion of the region of at least one of the first and second conducting layers, in contact with the first insulating layer, includes an amorphous conducting layer made of a semiconductor, and the amorphous conducting layer contains at least one element selected from the group consisting of oxygen, nitrogen, carbon, argon, chlorine, and fluorine and a total concentration of the at least one element falls within the range from 0.1 atomic % to 20 atomic %.
    Type: Grant
    Filed: August 23, 1996
    Date of Patent: February 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiko Saida, Yoshio Ozawa
  • Patent number: 5859451
    Abstract: A memory cell comprising a MOSFET formed on a principle surface of a semiconductor substrate and an information storage capacitor having a storage electrode formed in or on the substrate so as to contact with a drain region of the MOSFET, and a capacitor electrode formed adjacent to the storage electrode with a capacitor insulator film being sandwiched between the storage electrode and the capacitor electrode. The storage electrode is connected to the drain region of the MOSFET through a thin barrier layer which is formed between the drain region and the storage electrode region so as to prevent impurities in the storage electrode from being diffused into the drain region.
    Type: Grant
    Filed: June 19, 1991
    Date of Patent: January 12, 1999
    Assignee: NEC Corporation
    Inventor: Kaoru Narita
  • Patent number: 5854493
    Abstract: A superconducting device has a substrate, and a superconducting channel provided by an oxide superconductor thin film formed to have an angle with respect to a deposition surface of the substrate. A superconductor source electrode region and a superconductor drain electrode region are formed at opposite ends of the superconducting channel, so that a superconducting current can flow through the superconducting channel between the superconductor source electrode region and the superconductor drain electrode region. A gate electrode region is formed of a oxide superconductor thin film which is deposited in parallel to the deposition surface of the substrate and which has an end portion which abuts with an insulating layer which separates the end portion and the superconducting channel so as to control superconducting current flow through the superconducting channel.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: December 29, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5851440
    Abstract: A liquid crystal display apparatus has a display region in the substrate and a peripheral circuit region for driving the display region formed in the periphery, and monopolar thin film semiconductor elements and bipolar thin film semiconductor elements are formed in the peripheral circuit region and monopolar thin film semiconductor elements or bipolar thin film semiconductor elements are formed in the display region. In the semiconductor film of the monopolar semiconductor element and the bipolar semiconductor element, both of a zone containing a high concentration n-type impurity and a zone containing a high concentration p-type impurity are formed. The liquid crystal display apparatus consumes a small amount of electric power.
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: December 22, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Tanaka, Yoshiro Mikami
  • Patent number: 5849610
    Abstract: A method of constructing a planar equal path length clock tree. Prior computer-generated methods of creating low-skew clock trees required that clock sinks be uniformly distributed throughout the circuit. Moreover, the tree produced would often be non-planar, thus increasing layout design complexity and cost. The present invention provides for a method of automatically producing a planar clock tree with equal path lengths from each clock sink to the clock source. A first branch wire is formed between the clock source and the clock sink that is a farthest distance from the clock source. Thereafter, the remaining uncoupled clock sinks are coupled to the clock tree according to a maximum rule and a minimum rule. Thus a planar equal path length clock tree is formed. The planar equal path length clock tree is transformed in to a rectilinear clock tree, including horizontal and vertical wires, by using a line search algorithm.
    Type: Grant
    Filed: March 26, 1996
    Date of Patent: December 15, 1998
    Assignee: Intel Corporation
    Inventor: Qing Zhu
  • Patent number: 5847433
    Abstract: In an integrated switching circuit with a CMOS circuit and a method for producing isolated active regions of the CMOS circuit, a field plate is doped jointly with wells located beneath it, so that the field plate includes an n-doped region and a p-doped region, and a boundary layer forms in a transition region. Upon electrical connection of the field plate regions with the particular well located beneath them, a flat band condition prevails at a substrate surface.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: December 8, 1998
    Assignee: Siemens Aktiengesellschaft
    Inventor: Martin Kerber
  • Patent number: 5847424
    Abstract: A capacitor structure of a DRAM device and a method thereof, including a first electrode formed in each unit memory cell to be connected to a source of a transistor, a deteriorating prevention film formed at the lowermost surface of the first electrode, exclusive of a portion where the first electrode is connected to the source of a transistor, an underlayer formed beneath the deterioration prevention film, an undercut formed between the underlayer and deterioration prevention film, a high-dielectric film formed on surfaces of the first electrode, underlayer and deterioration prevention film which is exposed by the undercut, a reaction/diffusion prevention film formed on the high-dielectric film, formed on the first electrode and underlayer, exclusive of an area around the undercut, and a second electrode formed on the entire surface of the high-dielectric film and reaction/diffusion prevention film, thereby preventing increase of leakage current amount caused by the undercut formed during the capacitor manuf
    Type: Grant
    Filed: January 24, 1996
    Date of Patent: December 8, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho-kyu Kang
  • Patent number: 5844268
    Abstract: A select MOS transistor and a data storage MOS transistor are formed in an element region. The transistor has floating-gate electrodes. The floating-gate electrodes are spaced apart above the element region and connected to each other above a field region. Only a tunnel insulating film much thinner than a gate insulating film of the transistor is placed between the floating-gate electrode and a drain region. Only the gate insulating film much thinner than the gate insulating film of the transistor is placed between the floating-gate electrode and the channel region of the transistor. In the element region, the shape of a control electrode is the same as that of the floating-gate electrodes.
    Type: Grant
    Filed: November 1, 1996
    Date of Patent: December 1, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichiro Noda, Daisuke Tohyama
  • Patent number: 5841185
    Abstract: A semiconductor device comprises a semiconductor substrate having N- and P-channel regions formed therein; a plurality of first transistors formed in the N-channel region; a first field shield element-isolation structure having a first shield plate electrode and formed in the N-channel region for isolating the first transistors from each other; a plurality of second transistors formed in the P-channel region; and a second field shield element-isolation structure having a second shield plate electrode electrically connected to the first shield plate electrode and formed in the P-channel region for isolating the second transistors from each other; wherein respective values of a threshold voltage V.sub.tN of a parasitic transistor formed in a field region of the N-channel region, a threshold voltage V.sub.tP of a parasitic transistor formed in a field region of the P-channel region and a potential V.sub.sP of the first or second shield plate electrode are determined so as to meet V.sub.tN -V.sub.tP >V.sub.
    Type: Grant
    Filed: February 15, 1996
    Date of Patent: November 24, 1998
    Assignee: Nippon Steel Corporation
    Inventor: Akio Ishikawa
  • Patent number: 5838041
    Abstract: The present invention discloses a nonvolatile semiconductor memory device having a memory cell transistor in which an offset region is provided as a charge carrier injecting region. An insulating film and a gate electrode is formed in order of mention on a semiconductor substrate. Source/drain regions are formed on the surface of the semiconductor substrate with the gate electrode interposed therebetween. The drain has an LDD (Lightly Doped Drain) structure. Furthermore, a layered film of silicon oxide films and a SiN film is provided on a channel region between an edge of the gate electrode and a source diffusion layer. To be more specific, the layered film is formed in such a way that the SiN film is interposed between the silicon oxide films, constituting a side wall of the gate electrode. The SiN film is a charge carrier accumulating layer. Contact holes are formed in an insulating film between layers, respectively reaching the source and drain regions.
    Type: Grant
    Filed: October 2, 1996
    Date of Patent: November 17, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Sakagami, Kiyomi Naruke