Abstract: A resin or amorphous carbon layer is coated on a substrate and then fluorinated by exposing it in a F.sub.2 gas atmosphere. The thus fluorinated resin or amorphous carbon layer can be excellent in dielectric constant and thermal resistance. The resin may be photo-sensitive so that the resin can be patterned before the fluorination. Alternatively, the resin can be fluorinated before patterning.

Abstract: An optoelectronic semiconductor device using stimulated emission and absorption to achieve the functions of detection, modulation, generation and/or amplification of light. In one embodiment, the device includes a waveguide heterojunction bipolar transistor (HBT) biased in the active mode where the minority carrier concentration in the base is designed with bandgap engineering to optimize optical gain in this region. This HBT configuration allows optical modulation at considerably higher frequencies and/or with improved efficiency compared to the prior art, and is particularly suited to the fabrication of direct or external modulated wideband fiber optic links.

Abstract: A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars.

Abstract: An electronic device packaging structure is described which contains a lead frame on which the electronic device is disposed. The electronic device has contact locations at one edge thereof. The lead frame has leads which extend under the electronic device and inwardly from the opposite direction. Wires are wire bonded between electronic device contact locations and the beam leads which extend under the electronic device and the ends of the leads which extend inwardly from the opposite direction. Two electronic devices are stacked in at an offset with respect to each to expose contact locations on the surface of each electronic device at an edge of each electronic device to form a stepped surface exposing a plurality of electronic device contact locations. Preferably, the chips are identical and rotated 180.degree. with respect to each other.

Abstract: A bit-line pull-up circuit for an SRAM device which utilizes an improved diffusion structure for enhanced immunity of the SRAM device against electrostatic discharge. The improved diffusion structure includes an undivided diffusion region that serves as a common drain for a plurality of MOS transistors. The undivided diffusion region has at least a pair of recessed diffusion edges formed on opposite sides thereof. The forming of the recessed diffusion edges prevents the so-called electrical field crowding effect and also enhances ESD immunity for the MOS transistor. Further, since the drain diffusion region is an undivided area, an increased number of metal contact windows are provided therein, and at least one of the metal contact windows is arranged substantially between the two recessed diffusion edges. In the event of an electrostatic discharge, this allows the discharge current flowing into the drain to be divided into a greater number of small-magnitude currents flowing to the source.

Abstract: A compression bonded type semiconductor element having a ring-shaped gate terminal in the form of an annular metal disk projecting through the side of an insulating cylinder. The ring-shaped gate terminal includes an inner circumferential planar portion which is disposed so as to be slidable on an annular ring gate electrode. The annular ring gate electrode is in contact with a gate electrode formed on a semiconductor substrate, and the ring gate electrode is pressed against the gate electrode via the ring-shaped gate terminal by an elastic body.

Abstract: In a semiconductor device including a plurality of chip areas arranged in a matrix and a grid-like scribe areas a plurality of L-shaped alignment segments and a plurality of pairs of I-shaped alignment segments are provided within the scribe area. Each of the L-shaped alignment segments is located within a first quadrant defined by an X direction center line and a Y direction center line of the scirbe area, and each pair of the I-shaped alignment segments is located within a second quadrant defined by the X direction center line and the Y direction center line adjacent to the first quadrant.

Abstract: A semiconductor flash memory device comprises a substrate, a plurality of buried bit lines, an insulation film, a floating gate, an inter-layer insulation film, and a control gate formed on the inter-layer insulation film. The fabrication method comprises forming the patterned first insulation films on the substrate, forming the gate insulation film on the substrate and between the patterned first insulation films, depositing a first poly-silicon layer on the gate insulation film and the patterned first insulation film, forming a floating gate by etching the first poly-silicon layer, forming a second insulation film on each of the floating gate and the substrate having the buried bit lines therein, and forming a control gate on the second insulation film. The flash memory device realizes high yield rate due to the simplified fabrication steps and facilitated fabrication.

Abstract: The invention relates to a semiconductor device of the type sealed in glass, comprising a semiconductor body having a pn-junction between opposing faces which are connected to slugs of a transition metal, said slugs being connected to copper-containing connection conductors by a bonding layer, the bonding layer comprising, in addition to copper and silver, more than 1 wt. % germanium.

Abstract: A photodetector that incorporates at least two photosensitive regions (separated by at least one physical gap) of a first semiconductor type with the at least two photosensitive regions being supported on a substrate and acting as first terminals of the photodetector is improved by; adding a second semiconductor type into the physical gap(s) abutting the at least two photosensitive regions. The second semiconductor region(s) form a barrier to the out diffusion between the at least two photosensitive regions of the first semiconductor type. Additionally, the second semiconductor type region acts as a second photodetector terminal. This improved geometry results in faster rise and fall times of the photodetector's output current by decreasing the 3-D spaces within the gap(s) between the at least two photosensitive regions which were not subjected to the presence of an E-field when unimproved photodetectors were biased into operation.

Abstract: A ferroelectric memory cell integrated on a silicon substrate. The ferroelectric stack includes a ferroelectric layer, such as PbNbZrTiO, sandwiched between conductive metal-oxide electrodes, such as the perovskite LaSrCoO. The ferroelectric stack is grown over a barrier layer of an intermetallic alloy such as Ni.sub.3 Al or Ti.sub.3 Al, which is highly resistant to oxidation at elevated temperatures. The intermetallic layer is either deposited directly over the silicon substrate or over an intermediate TiN layer. The resulting structure does not require a platinum barrier layer.

Abstract: A field controlled semiconductor device of SiC has a drain, a highly doped substrate layer on top of the drain and a low doped n-type drift layer on top of the substrate layer. A p-type base layer is located on the drift layer and a vertical trench extends through the base layer. In the trench an n-type channel region extends vertically along a wall of the trench and connects a source region layer to the drift layer. A gate electrode is arranged in the trench to be on the opposite side of the channel region with respect to the base layer.

Abstract: A metal electrode disposed on a surface of an oxide superconductor and forming electric contact with the oxide superconductor wherein at least a portion of the metal electrode is in contact with a side surface of the oxide superconductor which is perpendicular to the surface on which the metal electrode is disposed.

Abstract: The present invention is directed to an improved trench MOS gate device that comprises a trench whose floor and sidewalls include layers of dielectric material, the layers each having a controlled thickness dimension. These thickness dimensions are related by a controlled floor to sidewall layer thickness ratio, which is established by individually controlling the thickness of each of the floor and sidewall dielectric layers. This floor to sidewall layer thickness ratio is preferably at least 1 to 1, more preferably at least 1.2 to 1. Further in accordance with the present invention, a process for forming an improved trench MOS gate device comprises etching a trench in a silicon device wafer and forming layers of dielectric material on the trench floor and on the sidewalls, each layer having a controlled thickness dimension. The thickness dimensions are related by a controlled floor to sidewall layer thickness ratio that is preferably at least 1 to 1.

Abstract: Disclosed is an integrated circuit configuration including a carrier having recesses for supporting individual semiconductor die units. The semiconductor die units and the carrier recesses have lithographically defined dimensions so as to enable precise alignment and a high level of integration.

Abstract: Producing a gap between a source and/or drain region of a silicon-on-insulator (SOI) field effect transistor which is less than the thickness of a depletion region normally surrounding the source and/or drain region, preferably at zero volts bias, permits gain of a parasitic bipolar transistor formed therewith to be transiently reduced and the effective base-emitter junction capacitance to be transiently increased during only modes of operation in which the parasitic bipolar conduction dominates normal operation of the field effect transistor. Such transient reduction of gain coupled with a transient reduction of high frequency response reduces the parasitic bipolar current spike to a degree greater than previously achievable and is fully compatible with other techniques of reducing such current spike.

Abstract: A semiconductor memory device includes a semiconductor substrate of a first conductivity-type, a first electrode formed on the semiconductor substrate for charging/discharging charges, a second electrode formed on the first electrode for controlling charging/discharging and data reading/writing of the first electrode, and a charge input/output stage formed on the semiconductor substrate on at least one side of the second electrode for supplying charges.

Abstract: An integrated circuit is described incorporating a substrate, a layer of insulator, a layer of silicon having raised mesas and thin regions therebetween to provide ohmic conduction between mesas, electronic devices on the mesas, and interconnection wiring. The invention overcomes the problem of a floating gate due to charge accumulation below the channel of MOS FET's.

Abstract: The degradation of integrity of the gate oxide in a CMOS transistor due to the formation of a tungsten silicide strapping layer on the polycrystalline silicon gate as a result of the migration of fluorine atoms from the tungsten hexafluoride used to form the tungsten silicide is reduced by increasing the dopant concentration of the polycrystalline silicon layer thereby to form dopant atoms in the grain boundaries of the polycrystalline silicon to block the migration of fluorine through the polycrystalline silicon to the underlying gate oxide. By preventing fluorine from reaching the gate oxide in this manner, the degradation of the gate oxide due to the replacement of oxygen by fluorine is decreased.

Abstract: A highly reliable semiconductor device with an increased life is provided as comprising a wiring substrate comprising a portion for mounting a semiconductor pellet, a semiconductor pellet mounted on the portion for mounting the semiconductor pellet, an electrode provided on the wiring substrate connected to an electrode of the semiconductor pellet, a layer comprising a sealing material which seals the semiconductor pellet and the electrode provided on the wiring substrate, wherein at least a through hole for discharging water vapor is formed in the portion for mounting the semiconductor pellet provided on the wiring substrate, and the protective film for preventing the adhesion of solder or plating is removed from not only the soldered or plated portion but also the periphery of the portion for mounting the semiconductor pellet.