Abstract: A semiconductor device wherein a sealing resin is filled in a space between an interconnecting wiring board and a semiconductor chip after the semiconductor chip is flip chip-mounted on the wiring board in which at least a non-planar region consisting of a through hole, a concave portion or a convex portion, or a region exhibiting poor wettability to the sealing resin is formed on the surface of the wiring board or the semiconductor chip so as to provide a void in the sealed resin filled between the wiring board and the semiconductor chip for the purpose of minimizing any bad influence from the sealing resin on the interconnecting wirings or elements formed on the semiconductor chip.

Abstract: An RF switch comprises a switching FET having gate and back gate terminals, an input port for receiving an RF signal, and an output port for providing substantially the RF signal during an ON state of the FET. Switching circuitry connects the back gate terminal of the FET to the input port during the ON state to reduce insertion loss during the ON state, and connects the back gate terminal to a point of reference potential during an OFF state of the FET to increase isolation during the OFF state. Preferably, the switching FET is a depletion mode silicon MOSFET capable of operating with low supply voltages. The switching circuitry preferably comprises a second FET for electrically connecting the back gate terminal and the input terminal (e.g., source) of the switching FET during the ON state, and a third FET for electrically connecting the back gate terminal of the switching FET to the point of reference potential during the OFF state.

Abstract: A MOSFET device structure, on a silicon on insulator layer, in which a body contact to the silicon on insulator layer exists, has been developed. The MOSFET device structure features a heavily doped P type body contact region in a lightly doped source and drain region of the MOSFET device structure, formed from an ion implantation through a metal silicide layer. The addition of the body contact results in more controllable device characteristics, in terms of drain currents, etc., than for counterparts fabricated in silicon on insulator layer, without the use of a body contact.

Abstract: Synapse can be formed from a smaller number of elements in a low-power semiconductor device, which realize a highly integrated neural network. Precise modifications of synapse weighting become possible and a neuron computer chip of a practical level can be accomplished.The semiconductor device includes a first electrode for charge injection, connected to a floating gate through a first insulating film; a second electrode for applying programming pulses, connected to the floating gate through a second insulating film, and a MOS transistor using the floating gate as its gate electrode, wherein the charge supplied from the source electrode of the MOS transistor sets the potential at the first electrode to a predetermined value determined by the potential of the floating gate, and charges are transferred between the floating gate and the first electrode through the first insulating film by applying a predetermined pulsating voltage to the second electrode.

Abstract: The present invention is directed to an exciplex formed from a .eta.-conjugated polymer and an electron donor or acceptor component. The present invention also relates to assemblies comprising said exciplex, their use in optoelectrical devices and method of enhancing optoelectrical properties of .eta.-conjugated polymers by forming said exciplex.

Abstract: A method for fabricating an integrated circuit capacitor having a dielectric layer comprising BST with excess B-site material, such as titanium, added. A polyoxyalkylated metal liquid precursor solution is prepared comprising a stock solution of BST of greater then 99.999% purity blended with excess B-site material such as titanium such that the titanium is in the range of 0-100 mol %. A xylene exchange is then performed to adjust the viscosity of the solution for spin-on application to a substrate. The precursor is spun on a first electrode, dried at 400.degree. C. for 2 minutes, then annealed at 650.degree. C. to 800.degree. C. for about an hour to form a layer of BST with excess titanium. A second electrode is deposited, patterned, and annealed at between 650.degree. C. to 800.degree. C. for about 30 minutes. The resultant capacitor exhibits an enlarged dielectric constant with only a small increase in leakage current.

Abstract: An embodiment of the instant invention is an ESD protection circuit (100) for protecting a circuit from negative stress, the ESD protection circuit comprising: a first terminal (102); a second terminal (104), the circuit to be protected connected between the first and the second terminals; a substrate (202) of a first conductivity type; a first doped region (206) of a second conductivity type opposite the first conductivity type and formed in the substrate, the first doped region forming the source of a transistor; a second doped region (208) of the second conductivity and formed in the substrate spaced from the first doped region by a channel region, the second doped region forming the drain of the transistor; a first diode region (210) of the first conductivity type and formed in the substrate, the first diode region being spaced a minimum distance from the second doped region and wherein the first diode region forms the anode of a diode (108) and the second doped region forms the cathode of the diode; and

Abstract: A light-emitting material for developing an organic EL device, which has the formula ?1! or ?2! recited in claims, and an organic EL device having layers thereof, the organic EL device having a high light emission brightness and a long life of light emission.

Abstract: Electron transporting layers comprised of organic free radicals are disclosed for use as the electron transporting layer in multi-layer structures that are useful for fabricating organic light emitting devices (OLEDs). For example, the multi-layer structure may include an electron transporting layer containing an organic free radical comprised of a multi-aryl-substituted cyclopentadienyl free radical of formula (I): ##STR1## wherein Ar.sub.1, Ar.sub.2, Ar.sub.3, Ar.sub.4 and Ar.sub.5 each are, independently of the other hydrogen, an alkyl group or an unsubstituted or substituted aromatic group. More specifically, included among these materials are those which are comprised of an electron transporting material based on, the pentaphenylcyclopentadienyl Cp.sup..phi..

Abstract: In a semiconductor memory device having a memory cell array and sense amplifiers connected by bit lines, a conductive shield plate is arranged over the bit lines and between the memory cell array and the sense amplifiers.

Abstract: A DRAM device structure, using a stacked capacitor configuration, has been developed. The stacked capacitor structure is comprised of a lower, polysilicon storage node, a thin composite dielectric layer, and an overlying capacitor plate, comprised of a composite layer of an overlying polysilicon layer, on a thin amorphous silicon layer, contacting an N type source and drain region, in a semiconductor substrate. A bit line contact structure, comprised of a metal silicide - polysilicon composite structure, is also used in the DRAM device structure. A PFET device, adjacent to the stacked capacitor DRAM device, featuring a two part contact structure, to P type source and drain regions, comprised of a wide top, aluminum - copper shape, overlying a narrower tungsten stud, is also used in this invention.

Abstract: A semiconductor device which includes a polysilicon gate separated from a semiconductor substrate by a re-oxidized nitrided oxide film in which the concentration of re-oxidized nitride in the film underlying the gate is non-uniform and in which the concentration of nitrogen in the substrate and the re-oxidized nitrided oxide along their interface and underlying the gate is non-uniform.Methods are disclosed of providing the non-uniform concentrations by incomplete shielding of the oxide by the gate during the nitriding and re-oxidizing process.

Abstract: The disclosure relates to a microcrystal silicon thin film transistor; The transistor includes a substrate, a gate electrode formed on the substrate, an insulating film formed on the substrate, a non-doped microcrystal silicon film formed on the insulating film, and source and drain electrodes which are formed on the microcrystal film. In the transistor, there is provided an ohmic contact between the source and drain electrodes through the microcrystal silicon film. The insulating film optionally has an etched surface layer prepared by etching the insulating film which has been formed on the substrate, with an aqueous solution containing HF. The TFT can be produced in a simple manner with safety and with a simple equipment.

Abstract: There is provided a semiconductor device including an upper wiring layer, a lower wiring layer, an interlayer insulating film sandwiched between the upper and lower wiring layers for electrically insulating the upper and lower wiring layers to each other, an insulating film formed on the interlayer insulating film, the insulating film being in planarized condition, and a wiring layer formed on a level with the insulating layer. The wiring layer horizontally surrounds a pit formed through the upper and lower wiring layers, the interlayer insulating film and the insulating film. Cut ends of the insulating film are exposed to a sidewall of the pit. Even if humidity is absorbed into the insulating film through the cut ends thereof exposed to the pit, humidity is not allowed to reach an internal circuit, because the insulating film is divided by the wiring layer. Thus, it is possible to prevent deterioration of performance and reliability of a semiconductor device which would be caused by humidity.

Abstract: A multiple crown shaped polysilicon structure, used for a lower electrode of a DRAM stacked capacitor structure, has been developed. The multiple crown shaped, lower electrode, is formed overlying, and contacting a polysilicon fill layer, that is located between insulator encapsulated polycide gate structures. The polysilicon fill layer, in turn, contacts an underlying source/drain region of a transfer gate transistor. The multiple crown shaped lower electrode is comprised vertical polysilicon shapes, connected to an underlying, horizontal polysilicon shape, with the horizontal polysilicon shape overlying the polysilicon fill layer. One to three, vertical polysilicon shapes, are used on each side of the multiple crown shaped lower electrode.

Abstract: A hermetically sealed ceramic integrated circuit package and method for achieving same, the package including an internal lead frame attached to an integrated circuit die in a lead-on-chip configuration, an external lead frame attached to the package exterior in a lead-on-package configuration and a high temperature adhesive layer which attaches the internal lead frame to the integrated circuit die.

Abstract: A MESFET structure (20) and a method that minimizes the effects of processing steps and device performance of the MESFET structure (20). The MESFET structure (20) has a gate (30) positioned over a channel region (28) and between a source region (36) and a drain region (34). The MESFET structure (20) further includes a hole injector region (32) formed near the channel region (28). The hole injector region (32) injects holes beneath the channel region (28) which decrease the ability of the trap sites to attract electrons generated by impact ionization. Thus, this supply of holes beneath the channel region (28) prevents the effects of IV-kink and hysteresis caused by electrons that are accumulated in the trap sites.

Abstract: An MOS transistor has a gate electrode is electrically conductively connected to an exposed contact area (pad). The contact area is electrochemically corrosion-resistant and is dimensioned for connection to a living cell. The surface topology is relatively flat and the surface, with the exception of the contact area, is protected with a dielectric passivation layer.

Abstract: A parasitic transistor of an insulated gate semiconductor device does not easily turn on, so that an SOA of the insulated gate semiconductor device is improved. P.sup.+ semiconductor layers (45) having a higher impurity concentration than that N.sup.+ emitter layers (44) are disposed so that the P.sup.+ semiconductor layers (45) overlap adjacent edges of the N.sup.+ emitter layers (44) of a U-type IGBT and so that bottom portions of the P.sup.+ semiconductor layers (45) contact P base layers (43). An emitter electrode (51) contacts the P base layers (43) through the P.sup.+ semiconductor layers (45). A trench pitch is small, and therefore, a parasitic transistor which is formed by an N.sup.+ emitter region (4), a P base layer (3) and an N.sup.- layer (2) does not easily turn on.

Abstract: A superconductor-insulator-superconductor Josephson tunnel junction, comprising: a single crystalline substrate having a perovskite crystal structure; a template layer formed of a b-axis oriented PBCO thin film on the substrate; and a trilayer structure consisting of a lower electrode, a barrier layer and an upper electrode, which serve as a superconductor, an insulator and a superconductor, respectively, the lower electrode and the upper electrode each being formed of an a-axis oriented YBCO superconducting thin film and having an oblique junction edge at an angle of 30.degree. to 70.degree., the barrier layer being formed of an insulating thin film between the two superconducting electrodes, can be operated at a low power with an exceptional speed in calculation and data processing.