Abstract: A parasitic transistor of an insulated gate semiconductor device does not easily turn on, so that an SOA of the insulated gate semiconductor device is improved. P.sup.+ semiconductor layers (45) having a higher impurity concentration than that N.sup.+ emitter layers (44) are disposed so that the P.sup.+ semiconductor layers (45) overlap adjacent edges of the N.sup.+ emitter layers (44) of a U-type IGBT and so that bottom portions of the P.sup.+ semiconductor layers (45) contact P base layers (43). An emitter electrode (51) contacts the P base layers (43) through the P.sup.+ semiconductor layers (45). A trench pitch is small, and therefore, a parasitic transistor which is formed by an N.sup.+ emitter region (4), a P base layer (3) and an N.sup.- layer (2) does not easily turn on.

Abstract: The semiconductor device disclosed has semiconductor patterns as elements constituting a semiconductor device on a semiconductor substrate. The semiconductor patterns are formed respectively on a first region and a second region on the semiconductor substrate. Between the first region and the second region, there is a stepped portion which is set such that a value S of the step is S=m.lambda./2n wherein .lambda. is a wavelength of the photosensitive illuminating light used in a photolithography process for patterning a photoresist film, m is a positive integer, and n is a refractive index of the photoresist film. The provision of the stepped portion enables the formation of semiconductor element patterns of fine sizes with controllability thereof.

Abstract: Flash EEPROM with NAND structure cells has a plurality of memory cell arrays. Each memory cell array has NAND structure of memory cell transistors arranged in column direction and connected serially. Each NAND structure cell has at its ends first and second select transistors, respectively. Control gates of corresponding cell transistors forming the NAND structure cells in respective memory cell arrays are connected together by control gate lines which are formed in row direction constituting word lines. Similarly, control gates of the first and second select transistors of respective memory cell arrays are connected respectively to first and second select gate lines parallel to the word lines.

Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.

Abstract: A nonvolatile semiconductor memory device including a plurality of memory cells, and a method of making this memory device.

Abstract: An insulation layer is formed on a silicon substrate. An SOI layer is formed on the insulation layer. A groove is selectively formed in the insulation layer. A bit line is buried in a lower half of the groove. A connection conductor layer is selectively formed on the side wall surface of the groove on the buried bit line. The SOI layer and the buried bit line are connected electrically via the connection conductor layer. A cap insulation layer is formed to fill the groove on the buried bit line in a region where said connection conductor layer is not formed.

Abstract: A compact contactless flash memory array for semiconductor EEPROM devices having a number of memory cell units. Field oxide layers for the flash memory array are first grown over the surface of an SOI wafer. Gate oxide layers are then grown. Floating gates are then formed by patterning the first polysilicon layer. Source/drain buried bitlines for the flash memory array are formed. A first BPSG (borophosphosilicate glass) layer is deposited and then reflown and etched back. An oxide-nitride-oxide layer is formed. A second polysilicon layer is deposited with in-situ dope. A WSi.sub.x layer then forms. Stacked gates for the flash array are formed by patterning into the formed oxide-nitride-oxide, second polysilicon and WSi.sub.x layers. The stacked gates are then covered with a second BPSG layer. Contact openings for the source/drain buried lines are formed.

Abstract: A compact contactless trenched flash memory array for semiconductor EEPROM devices is disclosed. The flash memory array comprises a number of memory cell units. Each of the cell units comprises a body line, source and drain regions and a stacked gate constructed over a silicon wafer substrate. The source and drain regions are buried regions and the body line is isolated by the surrounding buried source/drain regions and trenches formed to cut deep down to the substrate of the wafer. The stacked gate includes a first polysilicon layer, an oxide-nitride-oxide configuration, a second polysilicon layer, a pad oxide layer and a nitride layer. The source and drain buried regions sandwiches the body line, and the stacked gate substantially sits directly atop the body line. The flash memory array is free from the serious problem of short channel effect.

Abstract: After a MOS transistor having a gate electrode layer is formed on the surface of a semiconductor substrate, a first interlayer insulating film and a moisture blocking film are sequentially formed. After necessary contact holes are formed in the films, a first wiring layer is deposited and patterned together with the underlying blocking film, to form wiring layers for the connection to the transistor regions and a moisture blocking pattern covering the gate electrode layer. The first wiring layer includes a lowest Ti layer, Al alloy layer, and other layers. After a second interlayer insulating film is formed covering the first wiring layers, a second wiring layer is formed on the second interlayer insulating film. The second interlayer insulating film contains a spin-on-glass film which contains moisture.

Abstract: A technique for defining the active area of a high-T.sub.c superconductor Josephson junction uses an epitaxial slotted insulator patterned over the edge of the superconductor thin film-insulator bilayer. The superconductor/normal-metal/superconductor edge junction formed between the slotted insulator has a small active area. The counter electrode provided as an interconnect of the junction can therefore be wider than the active area of the edge junction since it can overlap onto the patterned slotted insulator. The use of the slotted insulator enables fabrication of junctions having resistances and critical currents in the desired range for high-T.sub.c superconductor circuits while enabling the use of wide, low inductance interconnects.

Abstract: The present invention relates to a transistor for providing protection from electrostatic discharge when a semiconductor device is exposed to electrostatic state, the transistor for providing protection from Electrostatic Discharge(ESD) being characterized by the fact that in case the gate length of a transistor is L, the gate length at the edges of the transistor is longer than the gate length L, and that the gate length is fixed as L and the edge of the transistor, in which the gate is adjacent to the active regions, has a grooved shape with an acute angle, and also the present invention makes the high-intensity electric field alleviated, and also enables the current to flow uniformly over the overall gate, and the heating effect is prevented, resulting in a prolonged life expectancy of the device.

Abstract: The multilevel embedded wiring system for an IC has a capping layer on the conductive layer in channels or trenches in insulating layers. The capping layer prevents halation of light in a lithography process, resulting in a high precision structure. Even if Cu is used as the conductive material, the resulting wiring resistivity is still low and the diffusion and oxidation of Cu are prevented.

Abstract: An inductor device with a MOS transistor internally installed is disclosed, in which an inductor can be arbitrarily connected in series or in parallel to the respective terminals of MOS transistors by applying a multi-layer wiring technique, thereby reducing the chip area. Within an inductor structure, MOS transistors which have an active region width of W .mu.m are formed in the number of n, and an inductor wire is connected to an arbitrary terminal of the MOS transistors by employing a multi-layer metal wiring process. Thus the inductor is connected to an arbitrary terminal of the MOS transistors in series. Thus an inductor device in which MOS transistors having a channel width of W.times.n .mu.m are internally installed is formed.

Abstract: A method for manufacturing a cap for use in a semiconductor package is disclosed. The semiconductor package includes a semiconductor chip and a substrate. The chip is mounted with the substrate at a chip locus. The method preferably comprises the steps of placing a slug in a die, and exercising the die to cold flow the slug to a predetermined cap configuration. The cap configuration includes a plurality of walls depending from a polygonal generally planar base and cooperating with the base to establish a well bounded by the walls and the base. The walls terminate in a plane, and the well clears the chip when the cap is mounted on the substrate at the chip locus. The invention further includes a cap for use in a semiconductor package. The cap comprises a structure cold flowed from a slug in a die to a predetermined cap configuration.

Abstract: A semiconductor device has a p-n-p transistor structure having a collector implemented by a p.sup.- -substrate, a base formed as an n-diffused region in the surface region of the substrate, and an emitter formed as a p.sup.+ -diffused region in the first n-diffused layer. The p.sup.- -substrate and the n-base are maintained at a ground level, while the p.sup.+ -collector is maintained at a positive potential for biasing the p-n junction formed between the emitter and the base. The bias potential allows the p-n-p transistor structure to operate in its saturation region to activate the base region to define an enlarged carrier-incresed zone. An analog input pad is located within the carrier-increased zone and protected from a noise propagated from a digital circuit section located outside the carrier-increased zone.

Abstract: The non-volatile memory has a storage cell complying with multi-bit data by means of a double layered floating gate architecture. The cell comprises: source 2 and drain 3 which are distant from each other along a direction L in a semiconductor substrate 1; a single first floating gate 4A which is provided between the source and the drain and above a principal plane of the semiconductor substrate and extends along a direction crossing the direction L; a control gate 5 which is placed between the drain ad source and above a principal plane of the first floating gate; high impurity concentration layers 21, 22 which are isolated from the source and drain in the semiconductor substrate; a plurality of second floating gates 4B.sub.1, 4B.sub.

Abstract: An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants in the substrate rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernable channel stops so that all cells falsely appear to have a common interconnection scheme. The camouflage is enhanced by providing a uniform pattern of metal leads over the transistor array, with a uniform pattern of heavily doped implant taps from the transistors for connection to the leads; undesired tap-lead connections are blocked by channel stops.

Abstract: This is a method of fabricating a bipolar transistor on a wafer. The method can comprise: forming a doped emitter contact layer 31 on a substrate 30; forming a doped emitter layer 32 on top of the emitter contact layer, the emitter layer doped same conductivity type as the emitter contact layer; forming a doped base epilayer 34 on top of the emitter layer, the base epilayer doped conductivity type opposite of the emitter layer; forming a doped collector epilayer 36, the collector epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming an collector contact 38 on top of the collector layer; forming a base contact 40 on top of the base layer; forming a emitter contact 44 on top of the emitter contact layer; and selective etching the emitter layer to produce an undercut 45 beneath the base layer.

Abstract: A memory cell having a storage capacitor structure which increases the capacitance by adding surface area to the storage electrode of the capacitor. A transfer transistor with a gate electrode and source-drain electrode areas is formed on a semiconductor substrate. An insulating layer is formed on the semiconductor substrate and the transfer transistor, which has a contact opening exposing one of the source-drain electrode areas as a contact area. A storage capacitor is formed on the insulating layer and electrically coupled to the contact area. The storage capacitor includes a first conductive layer with a vertical frame and at least one horizontal plate. The vertical frame is coupled to the contact area through the contact opening and one of the at least one horizontal plates has a plurality of extending areas which extend out vertically. The vertical frame, the at least one horizontal plate and the extending areas together form the storage electrode of the storage capacitor.

Abstract: A quantum dot logic unit (8) is provided which comprises a row of quantum dots (14, 16, and 18), with each quantum dot separated by vertical heterojunction tunneling barriers (20, 22, 24, and 26). Electric potentials placed on inputs (32, 34, and 36) are operable to modulate quantum states within the quantum dots, thus controlling electron tunneling through the tunneling barriers.