Abstract: The capacitor area is increased with a cylinder-shaped first storage electrode overlapped with a second electrode in an area which covers two adjacent cells. Included in a semiconductor device using the invention may be: a semiconductor substrate; a word line on the substrate; impurity regions at opposite sides of the word line in the substrate; a first contact hole on an odd impurity region; a first storage electrode connected to the first contact hole, which is overlapped with an adjacent even cell; a first sidewall storage electrode at opposite sides of the first storage electrode; a second contact hole on the even impurity region, the second contact hole having an insulated sidewall; a second storage electrode connected to the second contact hole, which is overlapped with an adjacent odd cell; a second sidewall storage electrode at opposite sides of the second storage electrode.

Abstract: A current limiter (15) is formed between a silicon substrate (10) and a source region (17) by a channel implant region (20). The channel implant region (20) is not modulated by a gate structure so the maximum voltage that can flow between the silicon substrate (10) and the source region (17) is determined by the doping profile of the ever-present channel implant region (20). A pinch-off structure (12) is used to form a depletion region which can support a large voltage potential between the silicon substrate (10) and the source region (17). In an alternate embodiment, a bipolar device is formed such that a limited current flow can be directed into a base region (32) which is used to modulate a current flow between silicon substrate (30) and an emitter region (38). Using the current limiters (15, 35) it is possible to form an AC current limiter (50) that will limit the current flow regardless of the polarity of the voltage placed across two terminals (51, 52).

Abstract: The integrated circuit package includes a package body, an integrated circuit chip enclosed airtight in the package body, a lead provided at a lower portion of the package body for connecting the integrated circuit chip to an external circuit, and air blasting means for cooling the package body by forced air cooling. The package body has, at an upper portion thereof, a heat radiation region formed from a fin and an air blasting region in which the air blasting means is disposed. A ventilation flue is formed between the heat radiation region and the air blasting region. This package is particularly superior in its heat radiation properties.

Abstract: A trench DMOS transistor includes a buried layer region formed between the drain region and overlying drift region and having a doping type the same as that of the drift region and drain region. The buried layer region is more highly doped than the drain region or drift regions and is formed by e.g. implantation prior to epitaxial growth of the overlying drift region. By providing an optimized doping profile for the buried layer region, it is ensured that avalanche breakdown occurs at the buried layer region/body region. Thus drain-source on resistance is reduced because the JFET region present in prior art devices is eliminated, while device ruggedness and reliability are enhanced.

Abstract: A structure for an improved solder terminal is disclosed. The improved solder terminal is made of a bottom metallic adhesion layer, a CrCu intermediate layer on top of the adhesion layer, a solder bonding layer above the CrCu layer and a solder top layer. The adhesion layer is either TiW or TiN. A process for fabricating an improved terminal metal consists of depositing an adhesive metallic layer, a layer of CrCu over the adhesive layer and a layer of solder bonding material, over which a solder layer is formed in selective regions and the underlying layers are etched using solder regions as a mask.

Abstract: The present invention provides a package for mounting of semiconductor device, wherein:(a) a power layer, a ground layer and a signal layer are laminated via an intermediate layer including an insulating layer,(b) the power layer and the ground layer are each constituted by an inner lead area, an outer lead area and an electro-conductive area, the inner lead area and the outer lead area being not covered with the intermediate layer and being exposed and the electro-conductive area being interposed between the inner lead area and the outer lead area and covered with the intermediate layer, and(c) substantially all of the electro-conductive area of each of the power layer and the ground layer is constituted by a planar electro-conductive member. In this package, the self-inductances of the power layer and the ground layer are low and the capacitor formed by these layers has a large capacity; therefore, the power line and ground line noise is reduced.

Abstract: A package for a high power semiconductor laser comprising a hermetically sealed container filled with a dry gaseous medium containing oxygen. The presence of oxygen in the laser atmosphere is counter to standard practice in the art which teaches the use of an atmosphere of a dry inert gas. The package also includes a getter for organic impurities, e.g., a getter composed of a porous silica or a zeolite. The hydrogen content of the materials used to form the package are reduced by baking at an elevated temperature for an extended period of time, e.g., at 150.degree. C. for 200 hours.

Abstract: A highly integrated semiconductor package having a light and compact construction and heat dissipating means suitable to effectively dissipate heat generated from the package during the operation of the package is disclosed. The semiconductor package has a lower heat sink for dissipating heat generated from a semiconductor chip of the package. The package also has a tape attached to the top of a plurality of inner leads of the package. The inner leads are attached to the top surface of the lower heat sink. The package further has a heat dissipating means for dissipating heat generated from the inner leads. The heat dissipating means has a heat bar attached to the tape. An upper heat sink may be integrated with the heat bar so as to form the heat dissipating means.

Abstract: A liquid crystal device includes a TFT or active element substrate on which TFTs and pixel electrodes are arranged in the form of a matrix, a counter substrate having a counter electrode formed thereon and arranged to oppose the active element substrate, a polymer dispersed liquid crystal layer arranged between the active element substrate and the counter substrate and having a polymer resin and a liquid crystal which are dispersed, and a fluorescent film arranged on the pixel electrode. The device displays an image by controlling scattering, absorption, and transmission of light passing through the polymer dispersed liquid crystal layer. The phosphor film converts part of supplied light into fluorescent light having a predetermined wavelength and outputs colored light. Light used for a display is increased in intensity by the fluorescent light emitted from the phosphor film, thereby displaying a bright image.

Abstract: A method of improving the performance of a traveling wave field-effect transistor operated at frequencies in the microwave range or above the microwave range comprising the steps of forming a depletion region beneath a gate electrode wherein, in a plane transverse to the direction of signal propagation, a depletion region edge has a first end portion located between the gate electrode and a drain electrode and a second end portion located between the gate electrode and a source electrode; and separating the depletion region edge from the drain electrode. Further improvements in the operation of the TWFET include adjusting the first end portion of the depletion region edge to be closer to the gate electrode relative to the distance between the second end portion of the depletion region edge and the gate electrode, controlling an effective conductivity of a semiconductor of the traveling-wave field effect transistor, and setting the length of the gate electrode at substantially 1.0 micron.

Abstract: An object of the present invention is to provide an LD-MOS transistor with a reduced device real estate and high breakdown strength. An extended drain region doped with phosphorus is formed in contact with an underside of an insulation layer and a drain diffusion region, respectively. The insulation layer is deposited over a conductive gate layer and a drain diffusion region, respectively.

Abstract: A HTSC Josephson device wherein the barrier layer is a cubic, conductive material.

Abstract: A method of making semiconductor quantum wires, and a light emitting device employing such wires, employs a semiconductor wafer as starting material. The wafer is weakly doped p type with a shallow heavily doped p layer therein for current flow uniformity purposes. The wafer is anodized in 20% aqueous hydrofluoric acid to produce a layer 5 microns thick with 70% porosity and good crystallinity. The layer is subsequently etched in concentrated hydrofluoric acid, which provides a slow etch rate. The etch increases porosity to a level in the region of 80% or above. At such a level, pores overlap and isolated quantum wires are expected to form with diameters less than or equal to 3 nm. When excited, the etched layer exhibits photoluminescence emission at photon energies well above the silicon bandgap (1.1 eV) and extending into the red region (1.6-2.0 eV) of the visible spectrum.

Abstract: A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.

Abstract: In accordance with the invention, electronic packages comprising a layer of molded plastic on one side of an insulating substrate are provided with a surrogate layer on the side of the substrate opposite the molded plastic to reduce bending stress. The surrogate layer is preferably thin, has a high coefficient of thermal expansion and is resistant to high tensile stress. Advantageously, the surrogate layer is processed concurrently with the molding of the plastic. Preferred surrogate layers are low temperature thermoplastic sheets, such as acetal plastic sheets, that soften at the molding temperature sufficiently to bond to the substrate. Alternatively, they can be higher temperature rigid materials, such as glass fiber composites, bonded to the substrate with an adhesive layer that cures during molding.

Abstract: An integrated circuit chip structure, which prevents electrical shorts between adjacent electrodes and contributes to miniaturization, and a method for forming an integrated circuit chip structure are provided. A first electrode of a predetermined pattern is formed on the integrated circuit chip and a second electrode is formed on a base in correspondence with the first electrode. A first adhesive made of elastomer is deposited on the second electrode and a conductive metal substance is coated thereon. Finally, the second electrode is joined with the first electrode by pressure, after a second adhesive is deposited on the upper surface of the metal substance.

Abstract: A heat sink fin assembly of the corrugated type for cooling an LSI package comprises a flat base plate and a heat dissipating member made of a thin metal sheet having convex and concave portions which are comprised of a repeated series of side wall portions, top portions, and bottom portions. The base plate and the heat dissipating member are integrated with each other by bonding.

Abstract: In a circuit board/IC package assembly the die cavity in the IC package body portion is filled with a thermally conductive liquid to substantially facilitate the transfer of operational die heat toward the inner, lid side of the IC package that faces the circuit board. To dissipate the die heat received by the die cavity lid, a spaced series of metal-plated through holes are formed in the circuit board. The metal plating portions of the through holes are engaged with an internal ground plane structure within the circuit board, and are thermally coupled to the IC package die cavity lid. Accordingly, during operation of the IC package, die heat is conducted to the ground plane structure sequentially through the die cavity liquid, the cavity lid, and the metal-plated through holes.

Abstract: Multichip integrated circuit modules having crossed bonding wires are disclosed together with methods of making the same. The integrated circuit dies of the multi-chip modules are affixed to a suitable die supporting substrate. The dies are then electrically coupled to each other and/or to associated lead traces by wire bonding the dies, with at least two of the bonding wires being crossed. The integrated circuit dies, the bonding wires, and at least a portion of the lead traces are enclosed in a package. In one embodiment, the bonding wires used in the wire bonding step are precoated with an insulating material. In another embodiment, the insulating layers are formed on the bonding wires after the wire bonding step to prevent shorting between the wires. The insulating layers may be formed in a variety of manners. By way of example, the wires can be oxidized, or they may be coated with a protective material.

Abstract: A process for applying a TiN contact/via adhesion layer to high aspect ratio contact/via openings etched in a dielectric comprises providing a first layer of TiN on the bottom of the contact/via openings and then depositing the second layer of TiN on the first layer of TiN and on the sidewalls of the contact/via openings. The second layer of TiN serves as the contact/via adhesion layer for structurally supporting the adhesion of a tungsten plug in the contact/via openings. In the case where a contact is etched in the dielectric down to a junction with a titanium silicide layer on top, the first layer of TiN on the bottom of the contact opening is provided by a rapid thermal anneal in a nitrogen-containing atmosphere which converts the top part of the titanium silicide layer in the contact into a barrier TiN layer.