Abstract: A Si IC includes an Al-based layer which is deposited as a composite of sublayers of different composition Al-based materials. In one embodiment a first sublayer comprises an Al-Si-based alloy disposed so as to prevent substantial Si migration into the first sublayer, and a second sublayer, above the first, comprises an Al-based alloy with substantially no Si to alleviate precipitation-induced problems.

Abstract: It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1.times.10.sup.18 /cm.sup.3 introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6').

Abstract: A semiconductor chip is positioned between encapsulating sheets. The encapsulating sheets each have a surface that is highly adhesive and a surface that is less adhesive. The surface of the encapsulating sheet that is highly adhesive contacts the chip. The surface that is less adhesive contacts a mold. Subsequently, encapsulation is carried out by molding. A soldering resistance can be improved without reducing a mold releasing property.

Abstract: An alloy-free pressure contact type semiconductor device maintains a high reliability during transportation even without a pressure contact tool such as a simplified stack and therefore does not require a high transportation cost. Through holes (H1) and (H2) each having a circular cross section are formed in distortion buffer plates (21A) and (21K) at the center. A first and a second bottomed holes (i.e., recesses) (N1) and (N2) are formed in an anode electrode plate (41A) and a cathode electrode plate (41K). From the through hole (H1) up to the first bottomed hole (N1), a pressure contact pin (9) biased by a coil spring (8) is disposed. From the through hole (H2) down to the second bottomed hole (N2), a fixing pin (90) is disposed. Without applying external pressure upon the device, it is possible to prevent displacement of the first and the second distortion buffer plates due to vibration or impact during transportation and damage to a semiconductor body.

Abstract: A multilayer interconnect structure for a semiconductor integrated circuit comprising a base layer of titanium, a second layer of titanium nitride, a third layer of an aluminum alloy and a top layer of titanium nitride. All of the layers contained within the multilayer interconnect structure are deposited by in-situ deposition in an ultra-high vacuum deposition system. The different layers deposited in the deposition system are conducted consecutively without a disruption to the vacuum. Although each layer in the multilayer interconnect structure are deposited within the integrated ultra-high vacuum deposition system, with multiple deposition chambers, the deposition of the different layers is conducted at different temperatures. The time to the electromigration failure of the multilayer interconnect structure, caused by the electromigration of the aluminum alloy, is greatly increased by depositing the aluminum alloy layer at a temperature in excess of 300.degree. C. and preferably between 350.degree. C.

Abstract: A non-volatile semiconductor memory device comprises a semiconductor substrate, a shield gate electrode formed over a device isolation region of the semiconductor substrate through a shield gate insulating film, a floating gate electrode formed over a device region of the semiconductor substrate through a tunnel insulating film, the device region lying adjacent to the device isolation region and a part of the floating gate electrode overlapping the device isolation region so as to form a gap region therebetween, and a control gate electrode formed over the floating gate electrode through an oxide/nitride/oxide (ONO) film and formed over the shield gate electrode through a shield cap insulating film such that a part of the control gate electrode extends into the gap region.

Abstract: An interconnection structure is provided which is simple in structure and is easily manufactured and in which stress generated in solder bumps is minimized. Pads of a semiconductor chip and pads of a substrate are connected to each other by solder bumps. The solder bumps are hourglass-shaped. Metal core members are provided in the solder bumps, respectively. The core member is constituted with a circular bottom portion and a circular pin portion. The core member is soldered to the pad of the semiconductor chip by solder.

Abstract: In a cooling structure for cooling circuit element modules that are mounted on a circuit board and has heat sinks, there are provided a main duct to which the circuit element modules are connected, and a coolant supplying device which is connected to the main duct and supplies a coolant to the main duct.

Abstract: The present invention is premised on a semiconductor device in which one semiconductor chip is mounted on each of both faces of a die pad of a lead frame. The semiconductor chips are disposed such that the projected lines, on the die pad, of the corresponding sides of the semiconductor chips, intersect with each other at an angle of 45.degree.. The tips of inner leads are located in the sides of a virtual octagon formed by outwardly enlarging an octagon formed by connecting, to one another, the apexes of the semiconductor chips. The sides of the virtual octagon are respectively opposite to the sides of the semiconductor chips. The number of the inner leads of which tips are located in each of the sides of the virtual octagon, is the same as the number of bonding pads disposed at each of the sides of the semiconductor chips.

Abstract: A chip carrier according to the present invention includes: a carrier body including an upper face, a lower face, and an internal conductor; and a plurality of terminal electrodes formed on the upper face of the carrier body, the plurality of terminal electrodes electrically connecting an LSI chip to the internal conductor. A plurality of concave portions for electrically connecting a plurality of electrodes on a circuit substrate to the internal conductor are provided on the lower face of the carrier body, the concave portions being electrically connected to the internal conductor.

Abstract: An integrated circuit structure is described wherein individual integrated circuit devices such as MOS or bipolar transistors are constructed on and in a semiconductor substrate and one or more layers of metal interconnects are constructed on and in a second substrate, preferably of similar thickness, and the two substrates are then aligned and bonded together to thereby provide electrical interconnections of individual integrated circuit devices on the semiconductor substrate with appropriate metal interconnects on the second substrate to provide the desired integrated circuit structure without, however, contributing unduly to the overall size of the integrated circuit structure comprising the die or chip.

Abstract: A high breakdown voltage semiconductor device comprising a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active layer formed on the insulating layer and made of a high resistance semiconductor of a first conductivity type, a first impurity region of the first conductivity type formed in the active layer, and a second impurity region of a second conductivity type formed in the active layer and spaced apart from the first impurity region by a predetermined distance. The first impurity region is formed of diffusion layers. The diffusion layers are superimposed one upon another and differ in diffusion depth or diffusion window width, or both.

Abstract: The present concepts include "1:1" uniax (40) with one conductive through-hole per chip connection site, "mirror chip" testing, heat-sink bonding to chips, avoiding contact with conductive cleaved edge of chip, indium solid columns, metal recessed (41) in the through-holes. All of these are subject to preferred materials (UPILEX polyimide) and techniques (U.V. laser ablation, minimum taper of holes).

Abstract: A semiconductor device includes a semiconductor chip having top and bottom surfaces, upper leads electrically coupled to the semiconductor chip, where a first gap is formed between the upper leads and the top surface of the semiconductor chip, lower leads electrically coupled to the semiconductor chip, where a second gap is formed between the lower leads and the bottom surface of the semiconductor chip, and an encapsulating resin which encapsulates the semiconductor chip so as to maintain the first and second gaps.

Abstract: A lead frame assembly for a semiconductor device includes a lead frame having a lead frame main body and a first welding region, and a die pad frame having a die pad frame main body, a die pad frame, and a second welding region for welding to the first welding region of said lead frame main body. At least one of the first and second welding regions includes a welding pad for welding to the other welding region and a support bridge connected between the welding pad and a respective frame main body, supporting the welding pad from the respective frame main body, the support bridge including an element for suppressing transmission of at least one of mechanical force, heat, and electrical current.

Abstract: An integrated circuit package having an internal cooling device. The integrated circuit package includes a thermoelectric device that operates according to the Peltier cooling effect. The thermoelectric device includes a first plate and a second plate that are thermally connected by a plurality of conducting elements. A package substrate is attached to the first plate such that a chamber is formed. The second plate is disposed within the chamber apart from the package substrate. The second plate is cooled when power is supplied to the thermoelectric device. By disposing an integrated circuit chip on the second plate and evaluating the chamber, the integrated circuit chip may be cooled to a sub-ambient temperature without internal or external condensation.

Abstract: When an abrupt voltage noise is applied across an anode electrode (A) and a cathode electrode (K), displacement currents (I.sub.10 to I.sub.30) which are responsive to junction capacitances (C.sub.10 to C.sub.30) of respective unit thyristors (ST.sub.1, ST.sub.2, MT) are generated. The displacement currents (I.sub.10 to I.sub.30) flow into a compensation electrode (C) through paths in a P base layer (2) having resistances (R.sub.10 to R.sub.30), and further flow to an external power source through the cathode electrode (K) which is short-circuited with the compensation electrode (C). The paths of the three displacement currents (I.sub.10 to I.sub.30) are separated from each other by resistances (R.sub.12, R.sub.23). Therefore, a forward bias voltage of a junction (D.sub.10) caused by the displacement current (I.sub.10) is attenuated by the displacement current (I.sub.20), while a forward bias voltage of a junction (D.sub.20) caused by the displacement current (I.sub.

Abstract: An SOI-MOS transistor structure is obtained which enables prevention of a substrate floating effect, reduction of the gate capacity and the contact resistance, and connection of two or more transistors in series. A semiconductor device including this transistor includes a pair of n.sup.+ type source/drain regions and a p.sup.+ type channel potential fixing region formed by dividing an active region by a first wiring and a second wiring, and a third wiring and a fourth wiring extending from respective side portions of the wirings. Since holes stored in an effective channel region flow in the p.sup.+ type channel potential fixing region, the substrate flowing effect can be prevented. Since one region of the pair of n.sup.+ type source/drain regions is wider than the other region, the contact resistance can be decreased. Further, since the gate wirings are not connected to each other, transistors can be connected in series.

Abstract: An increase in breakdown voltage of a semiconductor device upon which a layer of high resistance material, such as SIPOS, has been formed is achieved by controllably modifying the physical composition of the high resistance layer, for example by patterning a plurality of generally wedge-shaped apertures into the layer, so that the electric field in the underlying substrate is made more uniform across the surface of the device. This increase in uniformity in the radial direction effectively spreads out or reduces the field away from its normal peak region near the corner of the drain/substrate PN junction. In most versions of this device, an additional advantage--decreased leakage current--is realized.

Abstract: The present invention discloses the use of a dielectric substrate panel suitable for supporting a plurality of independently packaged ICs. The substrate panel has a plurality of conductive landings arranged on its top surface, a plurality of conductive contacts arranged on its bottom surface and a multiplicity of electrically conductive vias. The vias pass through the substrate panel and are arranged to interconnect selected landings with their associated conductive contacts. The top surface of the substrate panel also includes a number of die attach areas. During packaging, dies are secured to their associated die attach areas on the substrate panel and electrically coupled to appropriate conductive landings. An encapsulant is then formed over each of the dies for protection.