Abstract: A perimeter independent precision locating member (22) for a semiconductor chip (10) so that contact sites upon the chip will be reliably positioned relative to connection members (18), such as contacts or leads, so that the chip may be electrically engageable. The locating member (22) is disposed upon the surface of the semiconductor chip (10) at a specific position relative the contact sites within the perimeter (24) of the chip and being closely matable with a complementary portion of a housing that contains the connection members (18). The method of making the perimeter independent precision locating member (22) for a semiconductor chip (10) involves coating the chip with a layer of photocurable material, masking the material in relation to the contact sites so that the portion of the material that will become the locating member (22) is exposed, illuminating the exposed portion of the photocurable material, and stripping from the chip the uncured portion to define the locating member (22).

Abstract: The radiation shielded and packaged integrated circuit semiconductor device includes a lid secured to a base to enclose the integrated circuit die within, wherein the lid and the base are each constructed from a high-Z material to prevent radiation from penetrating therethrough. Another embodiment includes a die attach slug constructed from a high-Z material disposed between the integrated circuit die and a base, in combination with a high-Z material lid to substantially block incident radiation.

Abstract: A description is given of a switching device (1) comprising a transparent substrate (3), a reflective switching film (5) of yttrium having a thickness of 500 nm and a palladium layer (7) having a thickness of 5 nm. Using hydrogen gas at atmospheric pressure and at room temperature, a transparent, semiconductive film (5) of YH.sub.3 is formed, which is converted to a metallic mirror-like film (5) of YH.sub.2 by exposure to heat. The conversion of YH.sub.2 into YH.sub.3 is reversible and can for example be used in an optical switching element and in thin displays.

Abstract: A superconducting oxide thin film device is composed of a LaAlO.sub.3 substrate and a YBCO thin film with a BaCeO.sub.3 buffer layer disposed between the two. The adhesion between the film and the substrate is increased by the presence of the buffer layer. The buffer layer also inhibits peeling of the film from the substrate and diffusion of Ba from the film into the substrate.

Abstract: A semiconductor device of a structure in which lateral surfaces of a semiconductor element and an element supporting member are bonded to each other without resorting to use of a base member on which the semiconductor element is disposed. Since thicknesses of the base member and a bonding resin provides no contribution to overall thickness of the semiconductor device, reduction of thickness thereof by 30 to 40% is made possible. In dependent on configuration of the element supporting member, the semiconductor device can be applied to large size elements, lead-on-chip structure (LOC) and others.

Abstract: On a rear surface of a semiconductor (10), a contact layer (11), a diffusion preventing layer (12) and a solder joint layer (13) are formed, and this solder joint layer (13) is connected to a mount base (15) by a Pb-Sn solder layer (14). The contact layer (11) is formed of a rare earth metal, its silicide or a composite thereof, the diffusion preventing layer (12) is formed of a ferrous metal, and the solder joint layer (13) is formed of a Ni-Au alloy. By forming the diffusion preventing layer (12) using the ferrous metal, a diffusion of tin in a solder is prevented and by the solder joint layer (13) of the Ni-Au alloy, an excellent solder joint property can be maintained to reduce the number of laminated layers. Further, as a surface treated layer of at least one joint member, the Ni-Au alloy is used and by heating the semiconductor substrate via a solder foil in a reducing atmosphere a high airtightness is obtained.

Abstract: A semiconductor device is disclosed, which includes an insulating layer and an interconnection layer having a conductive layer provided over the insulating layer. The interconnection layer is patterned by photolithography. The device further includes a cap-metal layer, which is deposited on the conductive layer and suppresses reflection of light beams at the time of patterning the interconnection layer. The cap-metal layer has any one of the following structures: a double-layered structure having a titanium nitride layer and a titanium layer located between the titanium nitride layer and the conductive layer; a double-layered structure having a titanium nitride layer and an aluminum-titanium alloy layer located between the titanium nitride layer and the conductive layer; and a single-layered structure consisting essentially of an aluminum-titanium alloy. These design ensure accurate interconnection patterning in the photolithography, and provide improved EM and SM immunities of the interconnection.

Abstract: A semiconductor device of the present invention includes a plurality of lead terminals extending from only one side surface of a package main body having major surfaces and side surfaces, the lead terminal extending parallel to the major surface by a predetermined size and being substantially perpendicularly bent to project from the major surface by a predetermined size in a vertical mount type semiconductor device, or being substantially perpendicularly bent to project from the major surface by a predetermined size and bent again at a distal end portion in parallel to the major surface in a horizontal mount type semiconductor device, and a supporting means projecting from the package main body by substantially the same size as the projecting size of the lead terminals. A method of manufacturing the semiconductor device of the present invention includes the steps of lead frame formation, chip mounting and bonding, mold sealing, and lead terminal formation.

Abstract: A semiconductor device has a lattice-mismatched crystal structure including a semiconductor film formed on a substrate with an intervening buffer layer. The buffer layer has a plurality of layers, including first sublayers, or regions, in which an element that controls the lattice constant is provided in increasing mole fraction, and second sublayers, or regions, in which the lattice constant is maintained. The first sublayers and second sublayers are provided in alternating fashion. The resulting device has an increased electron mobility as compared with the prior art.

Abstract: A semiconductor apparatus includes a semiconductor element and a substrate having a substrate base and a thin-film multilayer interconnection layer formed on the substrate base. The thin-film multilayer interconnection layer has insulating layers and interconnection patterns. The insulating layers and the interconnection patterns are alternately layered. Each of the insulating layers includes a first insulating layer part and a second insulating layer part. A surface of the second insulating layer part is more flat than that of the first insulating layer part, and each of the interconnection patterns is arranged on the surface of the second insulating layer part.

Abstract: The invention provides a resin sealing type semiconductor device and fabrication method thereof. The resin sealing type semiconductor device has good heat radiation characteristics and high reliability. A highly flexible wiring arrangement design is provided by using leads commonly. The resin sealing type semiconductor device includes an element mounting portion having an element mounting surface. A semiconductor element is bonded to the element mounting surface. A plurality of leads is provided and is separated from the semiconductor element, a frame lead is disposed between these leads and the semiconductor element and not in contact with either the semiconductor element or the leads. Wires are provided for electrical connections and a resin seals the element mounting portion, the semiconductor element, parts of the leads and the frame lead.

Abstract: MOSFET and IGBT components protected against overvoltage by a limiting diode inserted between drain or, respectively, collector terminal and gate terminal are provided. A freewheeling diode connected to the component having a limiting diode with a breakdown voltage that is lower than the breakdown voltage of the freewheeling diode by a defined amount is provided. This over-voltage protection can be achieved in a simple way by integrating the limiting diode into the semiconductor body of the freewheeling diode and by a corresponding arrangement of the anode zone of the limiting diode.

Abstract: Provided is a press contact type semiconductor device which improves the shape of an insulator formed along an outer peripheral edge and a major surface of a semiconductor substrate, simplifies alignment of an anode heat compensator and a cathode heat compensator, causes no biting, causes no separation in molding, and has excellent heat dissipation. In the press contact type semiconductor device, the inner periphery of a ring-shaped insulator (22) which is formed along an edge of the overall periphery and a major surface of a semiconductor substrate (6) provided with a P-N junction in its interior comprises a tapered portion (22a) along the inner peripheral direction and a vertical portion (22b) forming a perpendicular inner peripheral diameter which is continuous to this tapered portion (22a).

Abstract: An array of programmable interconnect cells, each cell having a floating gate as the gate of an MOS switch transistor which programmably connect or disconnects nodes, is used in an FPGA. The floating gate of each cell, which is capacitively coupled to a control gate, is programmed by Fowler-Nordheim tunneling through an tunneling oxide above a programming/erase line in the integrated circuit substrate. Contiguous and parallel to the programming/erase line is at least one tunneling control line which forms a PN junction in close proximity to the programming/erase line region under the tunneling oxide. Under a reverse bias, a deep charge depletion region is formed in the programming/erase line region to block tunneling. In this manner, a selected cell can be programmed/erased, while the non-selected cells are not.

Abstract: A circuit connecting a sub-IGBT element S.sub.2 having a smaller current capacity and a smaller saturated current than the main IGBT element S.sub.1 and a resistance R.sub.1 in series is connected to the main IGBT element S.sub.1 in parallel, a MOSFET element S.sub.3 being connected between the gate electrode of the sub-IGBT element S.sub.2 and the emitter electrode of the main IGBT element S.sub.1, a delay element being connected between the gate electrode of the sub-IGBT element S.sub.2 and the gate electrode of the main IGBT element S.sub.1. In normal operation, the ON-state voltage is small and low loss can be realized. In the event of a short-circuit accident, the sub-IGBT element S.sub.2 detects the short-circuit before the main IGBT element S.sub.1 turns on to prevent an over-current from flowing in the main IGBT element S.sub.1, which substantially improves the short-circuit resistivity of the semiconductor device.

Abstract: A film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof wherein a plurality of chip semiconductor devices are laminated onto a substrate. Each chip semiconductor device includes a film carrier tape having leads, a semiconductor chip electrically connected to the leads, a heat sink mounted to a surface of the chip, and a connector for mounting the heat sink, the connector being electrically connected to the leads of the film carrier tape. The film carrier tape includes a carrier member having a metallic layer superposed thereon which is etched so as to form the leads and the heat sink.

Abstract: High-performance bipolar transistors with improved wiring options and fabrication methods therefore are set forth. The bipolar transistor includes a base contact structure that has multiple contact pads which permit multiple device layouts when wiring to the transistor. For example, a first device layout may comprise a collector-base-emitter device layout, while a second device layout may comprise a collector-emitter-base device layout. More specifically, the base contact structure at least partially surrounds the emitter and has integral contact pads which extend away from the emitter. Further, sections of the base contact structure are disposed on an insulating layer outside of the perimeter of the base region of the transistor, while other sections directly contact the base region. Specific details of the bipolar transistor, and fabrication methods therefore are also set forth.

Abstract: A structure for a read-only-memory (ROM) having both bipolar and channel transistors as memory cells to achieve efficient space utilization and higher density of ROM elements. The channel transistors include bit lines and word lines, with a threshold voltage at about 0.7 V. By implanting impurities into predetermined channel regions, memory cells become conductive or non-conductive. Bipolar transistors are formed in predetermined intersections of bit lines and word lines with a threshold voltage of about 3 V to 5 V, which can be treated as conductive memory cells that conduct current under 5 V operating voltage. Intersections of bit lines and word lines without bipolar transistors formed therein can be treated as non-conductive memory cells.

Abstract: A semiconductor device having N-type source and drain regions formed substantially in parallel to each other in the surface of a P-type semiconductor substrate. A channel region having first to fourth edges are sandwiched between each pair of the source and drain regions on the first and second edges. A gate insulating film is formed on the semiconductor substrate. Gate electrodes are formed substantially in parallel to each other on the semiconductor substrate via gate insulating film so as to cross the source and drain regions. The first and second edges of the channel regions are substantially parallel to the source and drain regions, and third and fourth regions are substantially parallel to the gate electrodes. A P-type impurity diffusion region is formed by ion implantation in accordance with self-alignment with gate electrode, at least on either of the third or fourth edge of at least one of the channel regions.

Abstract: A multi-chip packaging arrangement that contemplates stacking discrete components over film based components is disclosed. The multi-chip package includes a substrate having one or more film based components formed thereon. A discrete component is mounted on the substrate over the film based component such that it is electrically isolated from the film based component. One or more die components are also mounted on the substrate and a plurality of leads are provided for electrically connecting the multi-chip package to external circuitry. Wiring traces formed on the substrate are provided to electrically connect various ones of the components and the leads. A packaging material is provided to encapsulate the components and the wiring traces and leaves a portion of the leads exposed to facilitate electrically connecting the multi-chip package to external circuitry. Methods of making such multi-chip packages are also disclosed.