Abstract: The light receiving or back-side surface (22) of an indium antimonide (InSb) photodetector device (10) substrate (12) is cleaned to remove all native oxides of indium and antimony therefrom. A passivation layer (26) is then formed on the surface (22) of a material such as silicon dioxide, silicon suboxide and/or silicon nitride which does not react with InSb to form a structure which would have carrier traps therein and cause flashing. The device (10) is capable of detecting radiation over a continuous spectral range including the infrared, visible and ultraviolet regions.

Abstract: A semiconductor having multi-layer metalization which has a metal layer between aluminum alloy and metal nitride layers, that prevents failure of interconnects when electromigration causes a discontinuity in the aluminum alloy layer. In a one embodiment, the metal of the metal layer and the metal of the nitride layer are both the same metal, such as titanium. In a method of manufacturing the semiconductor device, an insulating layer is formed on a surface of a semiconductor substrate, and in vacuum chambers, the alloy layer is formed on the insulating layer, a metal layer is formed on the alloy layer, and a metal nitride layer is formed on the metal layer in an nitrogen atmosphere. Sputtering, such as DC magnetron sputtering, RF-bias sputtering, or thermal evaporation deposition, may be used to apply the respective nitride, metal and alloy layers.

Abstract: A Read-Only Memory (ROM) device produced by self-aligned implantation. First, a non-coded mask ROM with a silicon substrate, a plurality of bit-lines formed in the substrate, a gate oxide layer formed on the bit-lines, and a plurality of word-lines formed on the gate oxide, which together form arrays of memory cells, is provided. Next, an aligning layer is formed above the word-lines. A photoresist is thereafter coated on the surface of the aligning layer. Then, portions of the photoresist not covered by a mask pattern are etched away to the aligning layer so as to provide openings exposing portions of the memory cells that will be programmed to operate in a first conduction state. Portions of the aligning layer exposed through the openings are then removed, after which impurities are implanted through the openings and into the substrate to enable the memory cells that are to operate in the first conduction state, and leave other non-programmed memory cells operating in a second conduction state.

Abstract: An electronic chip component includes an electrode formed on a wafer, a passivation film formed on the wafer, and an organic protective film covering an entire surface of exposed portions of the electrode and the passivation film. A package for packing the component includes a carrier tape having therethrough a space for receiving the component with one end or side of the space opened, and a cover tape for closing the open end of the space after the component is stored in the space. A method for packing the component includes the steps of storing the component in the space of the carrier tape with one end of the space opened, and closing the open end of the space with the cover tape.

Abstract: A contact structure for an IC socket is usable for an IC package having a number of spherical type terminals or a number of cylindrical terminals arranged on the lower surface of an IC main body. To realize this contact structure for an IC socket, a number of contacts arranged corresponding to the spherical type terminals or the cylindrical terminals on the IC main body are provided. Resilient contact pieces for allowing each contact to come into pressure contact with each terminal at one point or at two points on the peripheral surface of the respective terminals are provided. Plural groups are constructed for a group of contacts and a group of terminals for changing an orientation of each resilient contact piece for allowing the group of contacts to give pressure contact force to the group of terminals in three directions or four directions. Each of the plural groups is arranged to generate an opposing force between adjacent groups.

Abstract: In order to maintain parasitic inductances of main electrodes at low levels also during operation of a semiconductor device, upright portions of main electrode plates serving as paths of main currents are sealed in a side wall portion of a resin case, whereby the main electrode plates are fixed to the case while being maintained in parallel with each other. Further, lower end portions are opposed in parallel with each other through a flat insulating spacer. Thus, parasitic inductances caused in the main electrode plates are suppressed. Further, the lower end portions are not fixed to a circuit board but electrically connected to a power transistor through wires. Therefore, no deformation of the main electrodes is brought by thermal deformation of the circuit board following heat generation of the transistor, whereby the parallelism of the main electrode plates is maintained also during the operation of the device.

Abstract: An integrated circuit package which has a plurality of inner surface pads located on a substrate and arranged in an angular pattern about an integrated circuit. The inner surface pads of the package are coupled to the outer surface pads of the integrated circuit with a TAB tape. The TAB tape has a plurality of conductors which each have a first end attached to the outer pads of the integrated circuit and a land portion attached to the inner surface pads of the substrate. The land portions of the tape are also arranged in an angular pattern about the integrated circuit.

Abstract: A thin film transistor (TFT) has first (lower) and second (upper) gate electrodes which are provided respectively above and under a semiconductor active layer and first and second insulating films (which serve as gate insulating films) provided respectively between the first gate electrode and a semiconductor layer and between a second gate electrode and the semiconductor layer. The second gate electrode has an anodic oxide film made of a material constituting the gate electrode on the upper and side surfaces thereof formed by anodization. Also, a silicide region is provided by covering the source/drain regions of the TFT with a silicide and changing a part of the region into a silicide.

Abstract: A semiconductor device comprising: (a) a semiconductor substrate on whose surface an integrated circuit is formed, (b) a first insulating layer formed on the semiconductor device and having first contact holes which lead to the integrated circuit, (c) a capacitance element formed on the first insulating layer, (d) a second insulating layer formed on the first insulating layer to cover the capacitance element, and having second contact holes which lead to an upper and a lower electrodes of the capacitance element respectively, and (e) interconnections which are connected to the integrated circuit and the capacitance element respectively through the first and second contact holes. The hydrogen density of this semiconductor device is 10.sup.11 atoms/cm.sup.2 or less.

Abstract: A thyristor according to the invention comprises a layer sequence containing an n-type emitter layer (4), a p-type base layer (5), an n-type base layer (6) and a p-type emitter layer (7) in a semiconductor substrate (3) between an anode (1) and a cathode (2). The p-type emitter layer (7) is perforated by anode short-circuit zones (8) and is thereby subdivided into sections. In this arrangement, the anode short circuits (8) short-circuit the n-type base layer (6) to the anode (1). Disposed between the anode short circuits (8) and the p-type emitter layer (7) is a p-type barrier layer (9), also referred to as p-type soft layer. According to the invention, said p-type barrier layer (9) has gaps (12) in which the n-type base (6) is contacted by the anode (1) either directly or via an anode short circuit (8).

Abstract: A semiconductor device includes a package accommodating a semiconductor chip, and a plurality of connecting leads. One end portion of each connecting lead being attached to the semiconductor chip by an adhesive member and the other end portion thereof being external to the package and connected to a circuit substrate. The semiconductor device further includes at least one heat-emitting lead whose one end portion is attached to the semiconductor chip by the adhesive member and whose other end portion is external to the package and is separated from the circuit substrate. The semiconductor device also includes a heat-emitting body inserted into the adhesive member and having one portion thereof connected to the heat-emitting lead.

Abstract: A thin film transistor comprises a dielectric substrate (1), a semiconductor layer (3) of poly-crystalline silicon layer having a drain region (8), an active gate region (4, 8-0), and a source region (7) placed on said substrate (1), a drain terminal (10) and a source terminal (10A) connected to said respective regions for external connection, a gate electrode (6) coupled with a part of said gate region (4) through a dielectric layer (4A), wherein length (d) of said gate electrode (6) is shorter than the length of gate region (4 plus 8-0), so that an offset region (8-0), where no gate electrode faces with said gate region, is produced.

Abstract: A p-type ohmic metal electrode for use with a group II-VI semiconductor device. The p-type ohmic metal electrode is made of a group II-IV p-type semiconductor layer having a group II element other than zinc dispersed in that layer disposed on the group II-IV semiconductor device, and a metal electrode layer disposed on the group II-IV semiconductor layer including the group II element other than zinc. Also disclosed is a group II-IV semiconductor device including a p-type group II-IV semiconductor containing zinc and selenium and the above ohmic metal electrode disposed on the group II-IV semiconductor device. Additionally, a group II-IV semiconductor device including a p-type group II-IV semiconductor containing zinc and selenium, a layer of a group II element other than zinc disposed on the group II-IV semiconductor device, and a metal electrode layer disposed on the layer of the group II element other than zinc is disclosed.

Abstract: Various techniques for forming superconductive lines are described whereby superconductive lines can be formed by stamping, etching, polishing, or by rendering selected areas of a superconductive film (layer) non-superconductive. The superconductive material can be "perfected" (or optimized) after it is formed into lines (traces). In one embodiment, trenches are etched in a substrate, the trenches are filled with superconductive material, and any excess superconductive material overfilling the trenches is removed, such as by polishing. In another embodiment, superconductive lines are formed by rendering selected areas of a superconductive layer (i.e., areas other than the desired superconductive lines) non-superconductive by "damaging" the superconductive material by laser beam heating, or by ion implantation. Superconductive lines formed according to the invention can be used to protect semiconductor devices (e.g.

Abstract: A semiconductor device implemented using a transistor (Q1) including at least one emitter (E1) and a transistor (Q2) which is larger than the transistor (Q1) including n emitters (E21 to E2n) each having the same area as the emitter (E1) of the transistor (Q1). The emitter (E1) of the transistor (Q1) is disposed between the emitters (E21 to E2n) of the transistor (Q2). When there is deflection of a substrate due to a stress to cause distortion in shape of the emitters, the emitter (E1) has much less distortion in shape than the emitters located on the end portions of the row region in the longitudinal direction. Since the transistor (Q2) has a number of emitters, the distortion in shape of the emitters (E21 to E2n) of the transistor (Q2), if any, has little effect on the whole.

Abstract: A semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. A PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14.

Abstract: An integrated circuit package assembly incorporating an electrostatic discharge (ESD) interposer is disclosed. The assembly includes a semiconductor chip including a plurality of chip input/output terminals. The interposer is formed using a substrate which supports the chip and includes an arrangement having a plurality of integrally formed ESD protection circuits for providing ESD protection to predetermined ones of the chip input/output terminals.

Abstract: The display apparatus of this invention performs a display by modulating the optical characteristics of a display medium.

Abstract: The present invention provides a MOS field effect transistor comprising: a semiconductor substrate having a first conductivity type; source/drain regions of a second conductivity type; lightly doped regions covering the bottom of the source/drain regions and surrounding the source/drain regions, the lightly doped regions having the second conductivity type and a lower impurity concentration than an impurity concentration of the source/drain regions; an off-set region surrounding the lightly doped regions, the off-set region having the first conductivity type, the off-set region having a lower impurity concentration than the impurity concentration of the lightly doped regions; and a channel stopper region having the first conductivity type, the channel stopper region having a higher impurity concentration than the impurity concentration of the off-set region, the channel stopper region surrounding the off-set region, the channel stopper region having projected portions under a gate electrode, the projected por

Abstract: A method for forming solder balls and an apparatus and method for forming solder columns on the electrical contact pads of an electronic package in order to establish a more reliable electrical and mechanical connection between an electronic package and a printed circuit board. In one embodiment, solder balls are formed on the electrical contact pads of a package by placing solder cylinders over the electrical contact pads and then passing the package through a reflow furnace where the solder cylinders take the form of spheres and are wetted onto the pads. In a second embodiment, a laminated solder column is formed that is resistant to collapse during the manufacturing process. The laminated solder column comprises a solder cylinder being clad on its top and bottom surfaces with a solder material having a lower melting temperature than that of the center solder cylinder.