Abstract: A method for forming the semiconductor device that includes forming a gate opening to a channel region of a fin structure; and forming a dielectric layer on the fin structure, in which an upper portion of the fin structure is exposed. A metal is formed within the gate opening. The portions of the metal directly contacting the upper surface of fin structure provide a body contact. The combination of the metal within the gate opening to the channel region of the fin structure and the dielectric layer provide a functional gate structure to the semiconductor device.

Abstract: A display device includes a substrate, a first insulating layer disposed on the substrate, a through portion passing through the substrate and the first insulating layer, a display unit disposed on the first insulating layer and including a plurality of pixels surrounding at least a portion of the through portion, and a dummy pixel unit. Each pixel includes a light-emitting element including a pixel electrode and an opposite electrode facing each other, and an emission layer disposed between the pixel electrode and the opposite electrode. The dummy pixel unit includes a plurality of dummy pixels disposed between the through portion and the display unit, and including a metal pattern including a same material as the pixel electrode. The dummy pixels are disposed adjacent to the display unit.

Abstract: A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

Abstract: Systems and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter, transmitter, and/or antenna can be positioned above a superconducting qubit chip having a Josephson junction coupled to a set of one or more capacitor pads. The radio frequency emitter, transmitter, and/or antenna can emit an electromagnetic signal onto the set of one or more capacitor pads. The capacitor pads can function as receiving antennas and therefore receive the electromagnetic signal. Upon receipt of the electromagnetic signal, an alternating current and/or voltage can be induced in the capacitor pads, which current and/or voltage thereby heat the pads and the Josephson junction. The heating of the Josephson junction can change its physical properties, thereby annealing the Josephson junction. In another example, the emitter can direct the electromagnetic signal to avoid unwanted annealing of neighboring qubits on the superconducting qubit chip.

Abstract: A method of forming a semiconductor device includes removing a top portion of a dielectric layer surrounding a metal gate to form a recess in the dielectric layer; filling the recess with a capping structure; forming a patterned hard mask over the capping structure and over the metal gate, wherein a portion of the metal gate, a portion of the capping structure, and a portion of the dielectric layer are aligned vertically with an opening of the patterned hard mask; and performing an etch process on said portions of the metal gate, the capping structure, and the dielectric layer that are aligned vertically with the opening of the patterned hard mask, wherein the capping structure has an etch resistance higher than an etch resistance of the dielectric layer during the etch process.

Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

Abstract: A semiconductor structure includes a first metal gate disposed over a first device region of a semiconductor substrate, where the first metal gate includes a first work function metal layer, a second metal gate disposed over a second device region of the semiconductor substrate, where the second metal gate includes a second work function metal layer, a first gate cut feature separating the first metal gate, where sidewalls of the first gate cut feature are defined by the first work function metal layer and a bulk conductive layer, and a second gate cut feature separating the second metal gate, where sidewalls of the second gate cut feature are defined by the second work function metal layer but not by the bulk conductive layer.

Abstract: A method for fabricating semiconductor devices at the wafer level, and devices fabricated using the method, are described. Wafer-level bonding using a relatively thick layer of electrically conducting bond medium was used to achieve void-free permanent wafer level bonding. The bond medium can be introduced to the pre-bonded wafers by deposition or as a preform. The invention provides a low cost, simple and reliable wafer bonding technology which can be used in a variety of device fabrication processes, including flip chip packaging.

Abstract: A method for fabrication a semiconductor device and a system utilizing the same are provided. In the method for fabrication the semiconductor device, at first, a semiconductor structure having a metal conducting structure is provided. Next, a dielectric layer is deposited over the metal conducting structure. Then, an etching process is performed on the dielectric layer by using a fluorine-containing gas so as to form an opening, in which fluorine-containing compounds are formed on a surface of the opening during the etching process. And then, a pre-cleaning process is performed by using UV radiation so as to remove the fluorine-containing compounds. After the pre-cleaning process is performed, a cleaning process is performed to clean the surface of the opening.

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

Abstract: According to another embodiment, a method of forming a transistor is provided. The method includes the following operations: providing a substrate; providing a source over the substrate; providing a channel connected to the source; providing a drain connected to the channel; providing a gate insulator adjacent to the channel; providing a gate adjacent to the gate insulator; providing a first interlayer dielectric between the source and the gate; and providing a second interlayer dielectric between the drain and the gate, wherein at least one of the formation of the source, the drain, and the channel includes about 20-95 atomic percent of Sn.

Abstract: A metal structure includes a patterned molybdenum tantalum oxide layer and a patterned metal layer. The patterned molybdenum tantalum oxide layer is disposed on a first substrate, in which the patterned molybdenum tantalum oxide layer includes about 2 to 12 atomic percent of tantalum. Both of an atomic percent of molybdenum and an atomic percent of oxygen of the patterned molybdenum tantalum oxide layer are greater than the atomic percent of tantalum of the patterned molybdenum tantalum oxide layer. The patterned metal layer is disposed on the patterned molybdenum tantalum oxide layer.

Abstract: In various embodiments, a layer of organic encapsulant is provided over a surface of an ultraviolet (UV) light-emitting semiconductor die, and at least a portion of the encapsulant is exposed to UV light to convert at least some of said portion of the encapsulant into non-stoichiometric silica material. The non-stoichiometric silica material includes silicon, oxygen, and carbon, and a carbon content of the non-stoichiometric silica material is greater than 1 ppm and less than 40 atomic percent.

Abstract: A method of manufacturing a semiconductor device in which a prescribed target lamination number of semiconductor chips are laminated on a substrate, the method includes: a first lamination step of laminating while temporarily bonding one or more semiconductor chips on the substrate to thereby form a first chip laminate body; a first permanent bonding step of pressurizing while heating from the upper side of the first chip laminate body to thereby collectively and permanently bond the one or more semiconductor chips; a second lamination step of sequentially laminating while temporarily bonding two or more semiconductor chips on the permanently bonded semiconductor chips to thereby form a second chip laminate body; and a second permanent bonding step of pressurizing while heating from the upper side of the second chip laminate body to thereby collectively permanently bond the two or more semiconductor chips.

Abstract: A method for manufacturing an OLED display panel is provided. The method includes steps of providing an array substrate; forming an OLED function layer including a first common layer, an organic light-emitting layer, and a second common layer on the array substrate; forming a first opening at a location near to the organic light-emitting layer using a first laser; forming a thin-film encapsulation layer on the OLED function layer; forming a second opening at a location corresponding to the first opening using a dry etching technique, the second opening passing through an inorganic layer of the thin-film encapsulation layer and at least one inorganic layer of the array substrate, and being connected to the first opening; and forming a perforated hole in the substrate at a location corresponding to the second opening using a second laser, thereby producing a through-hole in the OLED display panel.

Abstract: An OLED (organic light emitting diode) display panel is provided. The OLED display includes a substrate having a display region and a non-display region disposed around the display region, and the non-display region is provided with a partition wall. A first inorganic layer is disposed on the display region and the partition wall. A hydrophobic layer is disposed on the first inorganic layer and located corresponding to the partition wall. An organic layer is disposed on the first inorganic layer and a portion of the hydrophobic layer, wherein the organic layer is disposed on an inner side of the partition wall adjacent to the display region. A second inorganic layer is disposed on the organic layer.

Abstract: An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.

Abstract: Disclosed are a thin film transistor and a manufacture method thereof. The thin film transistor according to the embodiments of the present disclosure comprises: a base substrate; an active layer composed of polysilicon on the base substrate; and a first gate insulating layer having a preset intrinsic tensile stress on the active layer.

Abstract: Examples of the present disclosure provide power gating for stacked die structures. In some examples, a stacked die structure comprises a first die and a second die bonded to the first die. In some examples, a power gated power path is from a bonding interface between the dies through TSVs in the second die, a power gating device in the second die, and routing of metallization layers in the second die to the circuit region in the second die. In some examples, a power gated power path comprises a power gating device in a power gating region of the first die and is configured to interrupt a flow of current through the power gated power path to a circuit region in the second die.