Abstract: A technique disclosed in the Description relates to a technique for improving the heat dissipation capability of a semiconductor element and the heat dissipation capability of a lead electrode without increasing the size of a product. A semiconductor device of the technique includes the following: a semiconductor element; a lead electrode having a lower surface connected to an upper surface of the semiconductor element at one end of the lead electrode, the lead electrode being an external terminal; a cooling mechanism disposed on a lower surface side of the semiconductor element; and a heat dissipation mechanism provided to be thermally joined between the lower surface of the lead electrode and the cooling mechanism, the lower surface being more adjacent to an other-end side of the lead electrode than the one end, the heat dissipation mechanism including at least one insulating layer.

Abstract: Systems and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter, transmitter, and/or antenna can be positioned above a superconducting qubit chip having a Josephson junction coupled to a set of one or more capacitor pads. The radio frequency emitter, transmitter, and/or antenna can emit an electromagnetic signal onto the set of one or more capacitor pads. The capacitor pads can function as receiving antennas and therefore receive the electromagnetic signal. Upon receipt of the electromagnetic signal, an alternating current and/or voltage can be induced in the capacitor pads, which current and/or voltage thereby heat the pads and the Josephson junction. The heating of the Josephson junction can change its physical properties, thereby annealing the Josephson junction. In another example, the emitter can direct the electromagnetic signal to avoid unwanted annealing of neighboring qubits on the superconducting qubit chip.

Abstract: The present invention relates to a method for forming a layer, to be patterned, of an element by using a fluorinated material, which has orthogonality, and a solvent, the method comprising: a first step of printing with the fluorinated material so as to form, on a surface of a substrate, a mask template provided with an exposure part and a non-exposure part; a second step of coating the exposure part with a material to be patterned; a the third step of lifting-off the non-exposure part with the fluorinated solvent so as to form the layer to be patterned in the exposure part.

Abstract: A method is presented for preventing fin erosion. The method includes forming a plurality of hardmasks over a plurality of fin structures, trimming the plurality of fin structures such that the plurality of hardmasks are wider than the plurality of fin structures, forming a dielectric liner adjacent sidewalls of the plurality of fin structures, and depositing a dielectric between the plurality of fin structures. The method further includes directionally etching the dielectric to form recesses between the plurality of fin structures and isotropically etching dielectric remaining regions directly underneath the plurality of hardmasks such that upper corners of the plurality of fin structures remain in an undamaged state.

Abstract: The method comprises: forming an Al layer or Al droplets on a surface of a substrate by flowing an organic metal gas containing Al without flowing an ammonia gas; forming an AlN buffer layer on the Al layer or Al droplets by flowing the organic metal gas containing Al and the ammonia gas, the Al layer or Al droplets remaining as a metal under the AlN buffer layer; forming the Group III nitride semiconductor on the AlN buffer layer; and peeling the Group III nitride semiconductor in a place of the Al layer or Al droplets from the substrate.

Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

Abstract: An assembly used in a process chamber for depositing a film on a wafer and including a pedestal extending from a central axis. An actuator is configured for controlling movement of the pedestal. A central shaft extends between the actuator and pedestal, the central shaft configured to move the pedestal along the central axis. A lift pad is configured to rest upon the pedestal and having a pad top surface configured to support a wafer placed thereon. A pad shaft extends between the actuator and the lift pad and controls movement of the lift pad. The pad shaft is positioned within the central shaft and is configured to separate the lift pad from the pedestal top surface by a process rotation displacement when the pedestal is in an upwards position. The pad shaft is configured to rotate relative to the pedestal top surface between first and second angular orientations.

Abstract: The present disclosure provides a trench power semiconductor component and a method of making the same. The trench power semiconductor component includes a substrate, an epitaxial layer, and a trench gate structure. The epitaxial layer is disposed on the substrate, the epitaxial layer having at least one trench formed therein. The trench gate structure is located in the at least one trench. The trench gate structure includes a bottom insulating layer covering a lower inner wall of the at least one trench, a shielding electrode located in the lower half part of the at least one trench, a gate electrode disposed on the shielding electrode, an inter-electrode dielectric layer disposed between the gate electrode and the shielding electrode, an upper insulating layer covering an upper inner wall of the at least one trench, and a protection structure including a first wall portion and a second wall portion.

Abstract: A method of forming a semiconductor structure includes forming a metal gate stack over a shallow trench isolation (STI) material in a semiconductor substrate, forming an interlayer dielectric over the STI material, recessing the interlayer dielectric to a height lower than a top surface of the metal gate stack, forming a helmet structure over the recessed interlayer dielectric, and after forming the helmet structure, etching the metal gate stack until reaching the STI material.

Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

Abstract: A method of etching is described. The method includes forming a first chemical mixture by plasma-excitation of a first process gas containing an inert gas and at least one additional gas selected from the group consisting of He and H2, and exposing the first material on the substrate to the first chemical mixture to modify a first region of the first material. Thereafter, the method includes forming a second chemical mixture by plasma-excitation of a second process gas containing an inert gas and an additional gas containing C, H, and F, and exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material, which contains silicon oxide, relative to the second material and remove the modified first material from the first region of the substrate.

Abstract: Embodiments of the present disclosure provide an array substrate and a display apparatus having the array substrate. The array substrate includes: a plurality of pixel units which are arranged in an array and, which include a plurality of pixel electrodes arranged at intervals, respectively; a conductive layer disposed above or below two adjacent ones of the plurality of pixel electrodes, and configured such that when a preset electric potential is applied to the conductive layer, a first equivalent capacitance is formed between the conductive layer and a first one of the two adjacent pixel electrodes and a second equivalent capacitance is formed between the conductive layer and a second one of the two adjacent pixel electrodes.

Abstract: A method includes providing metal gate structures in a first and a second region, respectively, of a semiconductor substrate, simultaneously cutting the metal gate structures by a two-step etching process to form a first and a second trench in metal gate structures of the first and the second region, respectively, and filling each trench with an insulating material to form a first and a second gate isolation structure. Each step of the two-step etching process employs different etching chemicals and conditions. The metal gate structures in the first region and the second region differ in gate lengths and composition of gate electrode.

Abstract: A method for monitoring drift in a plasma processing chamber for semiconductor processing is provided. A plurality of cycles is provided, wherein each cycle comprises depositing a deposition layer over a chuck in the plasma processing chamber, plasma etching the deposition layer, and measuring a time for plasma etching the deposition layer to etch through the deposition layer. The measured time for plasma etching is used to determine plasma processing chamber drift.

Abstract: A method of identifying a wafer defect region is disclosed. The method includes preparing a sample wafer, forming a primary oxide film on the sample wafer at a temperature of 800° C. to 1000° C., forming a secondary oxide film on the primary oxide film at a temperature of 1000° C. to 1100° C., forming a tertiary oxide film on the secondary oxide film at a temperature of 1100° C. to 1200° C., removing the primary to tertiary oxide films, etching one surface of the sample wafer from which the primary to tertiary oxide films are removed to form haze on one surface of the sample wafer, and identifying a defect region of the sample wafer based on the haze.

Abstract: A method may include providing a substrate, comprising a patterning layer. The method may include forming a first pattern of first linear structures in the patterning layer, the first linear structures being elongated along a first direction. The method may include forming a mask over the patterning layer, the mask comprising a second pattern of second linear structures, elongated along a second direction, forming a non-zero angle with respect to the first direction. The method may include selectively removing a portion of the patterning layer while the mask is in place, wherein a first etch pattern is formed in the patterning stack, the first etch pattern comprising a two-dimensional array of cavities. The method may include directionally etching the first etch pattern using an angled ion beam, wherein a second etch pattern is formed, comprising the two-dimensional array of cavities, elongated along the first direction.

Abstract: A method for forming the semiconductor device that includes forming a gate opening to a channel region of a fin structure; and forming a dielectric layer on the fin structure, in which an upper portion of the fin structure is exposed. A metal is formed within the gate opening. The portions of the metal directly contacting the upper surface of fin structure provide a body contact. The combination of the metal within the gate opening to the channel region of the fin structure and the dielectric layer provide a functional gate structure to the semiconductor device.

Abstract: A method is provided for connecting a chip die to a circuit board with a capillary dispenser to deposit gold. The method includes forming a first bond by depositing gold from the dispenser to a board pad on the circuit board; forming a second bond by depositing the gold from the dispenser to a die pad on the chip die; extruding a filament of the gold by the dispenser in a normal direction from the second bond; rotating the filament laterally away from the first bond along a first radius; extruding the filament while rotating the filament towards the first bond along a second radius larger than the first radius; and forming a third bond by depositing the gold on the first bond to form a third bond.

Abstract: Methods and apparatus to form fully self-aligned vias are described. A seed gapfill layer is formed on a recessed first insulating layers positioned between first conductive lines. Pillars are formed from the seed gapfill layer and a second insulating layer is deposited in the gaps between pillars. The pillars are removed and a third insulating layer is deposited in the gaps in the second insulating layer to form an overburden of third insulating layer. A portion of the overburden of the third insulating layer is removed to expose the first conductive lines and form vias.

Abstract: A manufacturing method of a non-volatile memory structure including the following steps is provided. Memory cells are formed on a substrate. An isolation layer is formed between the memory cells. A shield electrode is formed on the isolation layer. The shield electrode is electrically connected to a source line.